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PDF DS1982 Data sheet ( Hoja de datos )

Número de pieza DS1982
Descripción 1-kbit Add-Only iButton
Fabricantes Dallas Semiconductor 
Logotipo Dallas Semiconductor Logotipo



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No Preview Available ! DS1982 Hoja de datos, Descripción, Manual

DS1982
1-kbit Add-Only iButtonTM
www.iButton.com
SPECIAL FEATURES
1024 bits Electrically Programmable Read-
Only Memory (EPROM) communicates with
the economy of one signal plus ground
EPROM partitioned into four 256-bit pages
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for randomly accessing packetized data
Each memory page can be permanently
write-protected to prevent tampering
Device is an “add only” memory where
additional data can be programmed into
EPROM without disturbing existing data
Architecture allows software to patch data by
superseding an old page in favor of a newly
programmed page
Reduces control, address, data, power, and
programming signals to a single data pin
8-bit family code specifies DS1982
communications requirements to reader
Reads over a wide voltage range of 2.8V to
6.0V from -40°C to +85°C; programs at
11.5V to 12.0V from -40°C to +50°C
COMMON iButton FEATURES
Unique, factory-lasered and tested 64-bit
registration number (8-bit family code +
48-bit serial number + 8-bit CRC tester)
assures absolute traceability because no two
parts are alike
F3 MICROCAN
0.36
3.10
0.51
c 1993
16.25
YYWW REGISTERED RR
97 09
000000FBC52B
17.35
Multidrop controller for MicroLAN
Digital identification and information by
momentary contact
Chip-based data carrier compactly stores
information
Data can be accessed while affixed to object
Economically communicates to bus master
with a single digital signal at 16.3 kbits per
second
Standard 16 mm diameter and 1-Wire®
protocol ensure compatibility with iButton
family
Button shape is self-aligning with cup-
shaped probes
Durable stainless steel case engraved with
registration number withstands harsh
environments
Easily affixed with self-stick adhesive
backing, latched by its flange, or locked with
a ring pressed onto its rim
Presence detector acknowledges when reader
first applies voltage
Meets UL#913 (4th Edit.); Intrinsically Safe
Apparatus, Approved under Entity Concept
for use in Class I, Division 1, Group A, B, C
and D Locations (application pending)
F5 MICROCAN
0.36
5.89
0.51
c 1993
16.25
YYWW REGISTERED RR
17 09
000000FBD8B3
17.35
DATA
GROUND
DATA
GROUND
All dimensions shown in millimeters.
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011800

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DS1982 pdf
HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2
DS1982
BUS
MASTER
OTHER
DEVICES
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COMMAND
LEVEL:
1-WIRE ROM FUNCTION
COMMANDS (SEE FIGURE 9)
DS 1982
AVAILABLE
COMMANDS:
READ ROM
MATCH ROM
SEARCH ROM
SKIP ROM
DATA FIELD
AFFECTED:
64-BIT ROM
64-BIT ROM
64-BIT ROM
N/A
DS1982-SPECIFIC
MEMORY FUNCTION
COMMANDS
(SEE FIGURE 6)
WRITE MEMORY
WRITE STATUS BYTE
READ MEMORY
READ STATUS BYTE
READ DATA/GENERATE
8-BIT CRC
1024-BIT EPROM
EPROM STATUS BYTES
1024-BIT EPROM
EPROM STATUS BYTES
1024-BIT EPROM
64-BIT LASERED ROM Figure 3
8-Bit CRC Code
48- Bit Serial Number
8- Bit Family Code (09h)
MSB
LSB MSB
LSB MSB
LSB
1-WIRE CRC GENERATOR Figure 4
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DS1982 arduino
DS1982
READ MEMORY [F0h]
The Read Memory command is used to read data from the 1024-bit EPROM data field. The bus master
follows the command byte with a 2-byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting
byte location within the data field. An 8–bit CRC of the command byte and address bytes is computed by
the DS1982 and read back by the bus master to confirm that the correct command word and starting
address were received. If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and
the entire sequence must be repeated. If the CRC received by the bus master is correct, the bus master
issues read time slots and receives data from the DS1982 starting at the initial address and continuing
until the end of the 1024-bit data field is reached or until a Reset Pulse is issued. If reading occurs
through the end of memory space, the bus master may issue eight additional read time slots and the
DS1982 will respond with an 8-bit CRC of all data bytes read from the initial starting byte through the
last byte of memory. After the CRC is received by the bus master, any subsequent read time slots will
appear as logical 1s until a Reset Pulse is issued. Any reads ended by a Reset Pulse prior to reaching the
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end of memory will not have the 8-bit CRC available.
Typically a 16-bit CRC would be stored with each page of data to ensure rapid, error-free data transfers
that eliminate having to read a page multiple times to determine if the received data is correct or not. (See
Book of DS19xx iButton Standards, Chapter 7 for the recommended file structure to be used with the 1-
Wire environment.) If CRC values are imbedded within the data, a Reset Pulse may be issued at the end
of memory space during a Read Memory command.
READ STATUS [AAh]
The Read Status command is used to read data from the EPROM Status data field. The bus master
follows the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a
starting byte location within the data field. An 8–bit CRC of the command byte and address bytes is
computed by the DS1982 and read back by the bus master to confirm that the correct command word and
starting address were received. If the CRC read by the bus master is incorrect, a Reset Pulse must be
issued and the entire sequence must be repeated. If the CRC received by the bus master is correct, the bus
master issues read time slots and receives data from the DS1982 starting at the supplied address and
continuing until the end of the EPROM Status data field is reached. At that point the bus master will
receive an 8-bit CRC that is the result of shifting into the CRC generator all of the data bytes from the
initial starting byte through the final factory-programmed byte that contains the 00h value.
This feature is provided since the EPROM Status information may change over time making it impossible
to program the data once and include an accompanying CRC that will always be valid. Therefore, the
Read Status command supplies an 8-bit CRC that is based on and always is consistent with the current
data stored in the EPROM Status data field.
After the 8-bit CRC is read, the bus master will receive logical 1s from the DS1982 until a Reset Pulse is
issued. The Read Status command sequence can be exited at any point by issuing a Reset Pulse.
READ DATA/GENERATE 8-BIT CRC [C3h]
The Read Data/Generate 8-bit CRC command is used to read data from the 1024-bit EPROM memory
field. The bus master follows the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8))
that indicates a starting byte location within the data field. An 8-bit CRC of the command byte and
address bytes is computed by the DS1982 and read back by the bus master to confirm that the correct
command word and starting address were received. If the CRC read by the bus master is incorrect, a
Reset Pulse must be issued and the entire sequence must be repeated. If the CRC received by the bus
master is correct, the bus master issues read time slots and receives data from the DS1982 starting at the
initial address and continuing until the end of a 32-byte page is reached. At that point the bus master will
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