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PDF DS1996 Data sheet ( Hoja de datos )
| Número de pieza | DS1996 | |
| Descripción | 64kbit Memory iButtonTM | |
| Fabricantes | Dallas Semiconductor | |
| Logotipo |  |
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www.dalsemi.com
SPECIAL FEATURES
§ 65536 bits of read/write nonvolatile memory
§ Overdrive mode boosts communication
speed to 142k bits per second
§ 256-bit scratchpad ensures integrity of data
www.DataSheet4U.com
transfer
§ Memory partitioned into 256-bit pages for
packetizing data
§ Data integrity assured with strict read/write
protocols
§ Operating temperature range from -40°C to
+70°C
§ Over 10 years of data retention
COMMON iButton FEATURES
§ Unique, factory-lasered and tested 64-bit
registration number (8-bit family code + 48-
bit serial number 8-bit CRC tester) assures
absolute traceability because no two parts are
alike
§ Multidrop controller for MicroLAN
§ Digital identification and information by
momentary contact
§ Chip-based data carrier compactly stores
information
§ Data can be accessed while affixed to object
§ Economically communicates to bus master
with a single digital signal at 16.3k bits per
second
§ Standard 16 mm diameter and 1-WireTM
protocol ensure compatibility with iButton
family
§ Button shape is self-aligning with cup-
shaped probes
§ Durable stainless steel case engraved with
registration number withstands harsh
environments
DS1996
64kbit Memory iButtonTM
F5 MICROCANTM
5.89
0.36
0.51
c 1993 16.25
YYWW REGISTERED RR
5E 0C
000000FBC52B
17.35
DATA
GROUND
All dimensions are shown in millimeters
§ Easily affixed with self-stick adhesive
backing, latched by its flange, or locked with
a ring pressed onto its rim
§ Presence detector acknowledges when reader
first applies voltage
§ Meets UL#913 (4th Edit); Intrinsically Safe
Apparatus, Approved under Entity Concept
for use in Class I, Division 1, Group A, B, C
and D Locations (application pending)
ORDERING INFORMATION
DS1996L-F5 F5 MicroCan
EXAMPLES OF ACCESSORIES
DS9096P
Self-Stick Adhesive Pad
DS9101
Multi-Purpose Clip
DS9093RA
Mounting Lock Ring
DS9093F
Snap-In Fob
DS9092
iButton Probe
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91099
1 page  
DS1996
MEMORY
The memory map in Figure 5 shows a 32-byte page called the scratchpad and additional 32-byte pages
called memory. The DS1996 contains 256 pages which comprise the 65536-bit SRAM. The scratchpad is
an additional page that acts as a buffer when writing to memory.
ADDRESS REGISTERS AND TRANSFER STATUS
Because of the serial data transfer, the DS1996 employs three address registers, called TA1, TA2 and E/S
(Figure 6). Registers TA1 and TA2 must be loaded with the target address to which the data will be
written or from which data will be sent to the master upon a Read command. Register E/S acts like a byte
counter and Transfer Status register. It is used to verify data integrity with Write commands. Therefore,
the master only has read access to this register. The lower five bits of the E/S register indicate the address
of the last byte that has been written to the scratchpad. This address is called Ending Offset. Bit 5 of the
www.DataShEe/eSt4Ure.cgoimster, called PF or ”partial byte flag,” is set if the number of data bits sent by the master is not an
integer multiple of 8. Bit 6, OF or ”Overflow,” is set if more bits are sent by the master than can be stored
in the scratchpad. Note that the lowest five bits of the target address also determine the address within the
scratchpad, where intermediate storage of data will begin. This address is called byte offset. If the target
address for a Write command is 13CH for example, then the scratchpad will store incoming data
beginning at the byte offset 1CH and will be full after only four bytes. The corresponding ending offset in
this example is 1FH. For best economy of speed and efficiency, the target address for writing should
point to the beginning of a new page, i.e., the byte offset will be 0. Thus the full 32-byte capacity of the
scratchpad is available, resulting also in the ending offset of 1FH. However, it is possible to write one or
several contiguous bytes somewhere within a page. The ending offset together with the Partial and
Overflow Flag is mainly a means to support the master checking the data integrity after a Write
command. The highest valued bit of the E/S register, called AA or Authorization Accepted, acts as a flag
to indicate that the data stored in the scratchpad has already been copied to the target memory address.
Writing data to the scratchpad clears this flag.
WRITING WITH VERIFICATION
To write data to the DS1996, the scratchpad has to be used as intermediate storage. First the master issues
the Write Scratchpad command to specify the desired target address, followed by the data to be written to
the scratchpad. In the next step, the master sends the Read Scratchpad command to read the scratchpad
and to verify data integrity. As preamble to the scratchpad data, the DS1996 sends the requested target
address TA1 and TA2 and the contents of the E/S register. If one of the flags OF or PF is set, data did not
arrive correctly in the scratchpad. The master does not need to continue reading; it can start a new trial to
write data to the scratchpad. Similarly, a set AA flag indicates that the Write command was not
recognized by the iButton. If everything went correctly, all three flags are cleared and the ending offset
indicates the address of the last byte written to the scratchpad. Now the master can continue verifying
every data bit. After the master has verified the data, it has to send the Copy Scratchpad command. This
command must be followed exactly by the data of the three address registers TA1, TA2 and E/S as the
master has read them verifying the scratchpad. As soon as the iButton has received these bytes, it will
copy the data to the requested location beginning at the target address.
MEMORY FUNCTION COMMANDS
The “Memory Function Flow Chart” (Figure 7) describes the protocols necessary for accessing the
memory. An example follows the flowchart. The communication between master and DS1996 takes place
either at regular speed (default, OD=0) or at Overdrive Speed (OD=1). If not explicitely set into the
Overdrive Mode the DS1996 assumes regular speed.
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DS1996
Match ROM [55H]
The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a
specific DS1996 on a multidrop bus. Only the DS1996 that exactly matches the 64-bit ROM sequence
will respond to the subsequent memory function command. All slaves that do not match the 64-bit ROM
sequence will wait for a reset pulse. This command can be used with a single or multiple devices on the
bus.
Skip ROM [CCH]
This command can save time in a single drop bus system by allowing the bus master to access the
memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus
and a read command is issued following the Skip ROM command, data collision will occur on the bus as
multiple slaves transmit simultaneously (open drain pulldowns will produce a wired–AND result).
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Search ROM [F0H]
When a system is initially brought up, the bus master might not know the number of devices on the 1-
Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process
of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM process
is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the
desired value of that bit. The bus master performs this simple, 3-step routine on each bit of the ROM.
After one complete pass, the bus master knows the contents of the ROM in one device. The remaining
number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the
Book of DS19xx iButton Standards for a comprehensive discussion of a search ROM, including an actual
example.
Overdrive Skip ROM [3CH]
On a single-drop bus this command can save time by allowing the bus master to access the memory
functions without providing the 64-bit ROM code. Unlike the normal Skip ROM command the Overdrive
Skip ROM sets the DS1996 in the Overdrive Mode (OD=1). All communication following this command
has to occur at Overdrive Speed until a reset pulse of minimum 480 µs duration resets all devices on the
bus to regular speed (OD=0).
When issued on a multidrop bus this command will set all Overdrive-capable devices into Overdrive
mode. To subsequently address a specific Overdrive-capable device, a reset pulse at Overdrive speed has
to be issued followed by a Match ROM or Search ROM command sequence. This will shorten the time
for the search process. If more than one slave supporting Overdrive is present on the bus and the
Overdrive Skip ROM command is followed by a read command, data collision will occur on the bus as
multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-AND result).
Overdrive Match ROM [69H]
The Overdrive Match ROM command, followed by a 64-bit ROM sequence transmitted at Overdrive
Speed, allows the bus master to address a specific DS1996 on a multidrop bus and to simultaneously set it
in Overdrive Mode. Only the DS1996 that exactly matches the 64-bit ROM sequence will respond to the
subsequent memory function command. Slaves already in Overdrive mode from a previous Overdrive
Skip or Match command will remain in Overdrive mode. All other slaves that do not match the 64-bit
ROM sequence or do not support Overdrive will return to or remain at regular speed and wait for a reset
pulse of minimum 480 µs duration. The Overdrive Match ROM command can be used with a single or
multiple devices on the bus.
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11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet DS1996.PDF ] | |
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