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PDF ET1011 Data sheet ( Hoja de datos )
| Número de pieza | ET1011 | |
| Descripción | A gigabit Ethemet transceiver | |
| Fabricantes | Agere Systems | |
| Logotipo |  |
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Preliminary Data Sheet
April 2004
TruePHY ™ ET1011
Gigabit Ethernet Transceiver
Features
■ 10Base-T, 100Base-TX, and 1000Base-T
gigabit Ethernet transceiver:
— 0.13 µm process
www.DataSheet4U.com — 128-pin TQFP:
❏ RGMII, GMII, MII, RTBI, and TBI interfaces to
MAC or switch
— 68-pin MLCC:
❏ RGMII and RTBI interfaces to MAC or switch
■ Low power consumption:
— Less than 750 mW in 1000Base-T mode
— Advanced power management
— ACPI compliant wake-on-LAN support
■ Oversampling architecture to improve signal integ-
rity and SNR
■ Optimized, extended performance echo and NEXT
filters
■ All digital baseline wander correction
■ Digital PGA control
■ On-chip diagnostic support
■ Automatic speed negotiation
■ Automatic speed downshift
■ Single supply 3.3 V or 2.5 V operation:
— On-chip regulator controllers
— 3.3 V or 2.5 V digital I/O
— 1.0 V core power supplies
— 1.8 V or 2.5 V for transformer center tap
■ JTAG
Introduction
Agere Systems ET1011 is a gigabit Ethernet trans-
ceiver fabricated on a single CMOS chip. Packaged
in either a 128-pin TQFP or a 68-pin MLCC, the
ET1011 is built on 0.13 µm technology for low power
consumption and application in server and desktop
NIC cards. It features single power supply operation
using on-chip regulator controllers. The 10/100/
1000Base-T device is fully compliant with IEEE®
802.3, 802.3u, and 802.3ab standards.
The ET1011 uses an oversampling architecture to
gather more signal energy from the communication
channel than possible with traditional architectures.
The additional signal energy or analog complexity
transfers into the digital domain. The result is an ana-
log front end that delivers robust operation, reduced
cost, and lower power consumption than traditional
architectures.
Using oversampling has allowed for the implementa-
tion of a fractionally spaced equalizer, which provides
better equalization and has greater immunity to tim-
ing jitter, resulting in better signal-to-noise ratio
(SNR) and thus improved BER. In addition,
advanced timing algorithms are used to enable oper-
ation over a wider range of cabling plants.
1 page  
Preliminary Data Sheet
April 2004
TruePHY ET1011
Gigabit Ethernet Transceiver
Functional Description (continued)
Transmit Functions
1000Base-T Encoder
In 1000Base-T mode, the ET1011 translates 8-bit data
from the MAC interfaces into a code group of four qui-
nary symbols that are then transmitted by the PMA as
4D five-level PAM signals over the four pairs of CAT-5
cable.
100Base-TX Encoder
www.DataSheet4U.com
In 100Base-TX mode, 4-bit data from the media inde-
pendent interface (MII) is 4B/5B encoded to output
5-bit serial data at 125 MHz. The bit stream is sent to a
scrambler, and then encoded to a three-level MLT3
sequence that is then transmitted by the PMA.
10Base-T Encoder
In 10Base-T mode, the ET1011 transmits and receives
Manchester-encoded data.
Receive Functions
Decoder 1000Base-T
In 1000Base-T mode, the PMA recovers the 4D PAM
signals after compensating for the cabling conditions.
The resulting code group is decoded to 8-bit data. Data
stream delimiters are translated appropriately, and the
data is output to the receive data pins of the MAC
interfaces. The GMII receive error signal is asserted
when invalid code groups are detected in the data
stream.
Decoder 100Base-TX
In 100Base-TX mode, the PMA recovers the three-
level MLT3 sequence that is descrambled and 5B/4B
decoded to 4-bit data. This is output to the MII receive
data pins after data stream delimiters have been trans-
lated appropriately. The MII receive error signal is
asserted when invalid code groups are detected in the
data stream.
Decoder 10Base-T
In 10Base-T mode, the ET1011 decodes the Manches-
ter-encoded received signal.
Hybrid
The hybrid subtracts the transmitted signal from the
input signal allowing full-duplex operation on each of
the twisted-pair cables.
Programmable Gain Amplifier (PGA)
The PGA operates on the received signal in the analog
domain prior to the analog-to-digital converter (ADC).
The gain control module monitors the signal at the out-
put of the ADC in the digital domain to control the PGA.
It implements a gain that maximizes the signal at the
ADC while ensuring that no hard clipping occurs.
Clock Generator
A clock generator circuit uses the 25 MHz input clock
signal and a phase-locked loop (PLL) circuit to gener-
ate all the required internal analog and digital clocks. A
125 MHz system clock is also generated and is avail-
able as an output clock.
Analog-to-Digital Converter
The ADC operates at 250 MHz oversampling at twice
the symbol rate in 1000Base-T and 100Base-TX. This
enables innovative timing recovery and fractional skew
correction and has allowed transfer of analog complex-
ity to the digital domain.
Timing Recovery/Generation
The timing recovery and generator block creates trans-
mit and receive clocks for all modes of operation. In
transmit mode, the 10Base-T and 100Base-TX modes
use the 25 MHz clock input. While in receive mode, the
input clock is locked to the receive data stream.
1000Base-T is implemented using a master-slave tim-
ing scheme, where the master transmit and receive are
locked to the 25 MHz clock input, and the slave
acquires timing information from the receive data
stream. Timing recovery is accomplished by first
acquiring lock on one channel and then making use of
the constant phase relationship between channels to
lock on the other pairs, resulting in a simplified PLL
architecture. Timing shifts due to changing environ-
mental conditions are tracked by the ET1011.
Agere Systems Inc.
5
5 Page 
Preliminary Data Sheet
April 2004
TruePHY ET1011
Gigabit Ethernet Transceiver
Functional Description (continued)
LEDs
Seven status LEDs are provided. These can be used to
indicate speed of operation, duplex mode, link status,
etc. There is a very high degree of programmability
allowed. Hence, the LEDs can be programmed to dif-
ferent status functions from their default value, or they
can be controlled directly from the MII register inter-
face. The LED signal pins can also be used for gen-
eral-purpose I/O if not needed for LED indication.
www.DataSheet4U.cNomote: The 68-pin MLCC has only two LEDs. Both can
be programmed through MII register 28 to pro-
vide all speed indications as well as link and
activity indications.
Resetting the ET1011
The ET1011 provides the ability to reset the device by
hardware (pin RESET_N) or via software through the
management interface. A hardware reset is accom-
plished by driving the active-low pin RESET_N to
0 volts for a minimum of 1 µs. The configuration pins
and the physical address configuration are read during
a hardware reset.
A software reset is accomplished by setting bit 15 of
the control register (MII register address 0 bit 15). The
configuration pins and the physical address configura-
tion are not read during software reset.
Low-Power Modes
The ET1011 supports a number of powerdown modes.
Hardware Powerdown Mode
Hardware powerdown is entered when the COMA sig-
nal is driven high. In hardware powerdown, all PHY
functions (analog and digital) are disabled. During
hardware powerdown, SYS_CLK is not available and
the MII registers are not accessible.
At exit from hardware powerdown, the ET1011 does
the following:
■ Initializes all analog circuits including the PLL.
■ Initializes all digital logic and state machines.
■ Reads and latches the PHY address pins.
■ Initializes all MII registers to their default values (H/W
configuration pins are reread).
Agere Systems Inc.
Software Powerdown Mode
Software powerdown is entered when bit 11 of the con-
trol register (MII register address 0 bit 11) is set. In soft-
ware powerdown, all PHY functions except the serial
management interface and clock circuitry are disabled.
The MII registers can be read or written. If the system
clock output is enabled (MII register address 22 bit 4),
the 125 MHz system clock will still be available for use
by the MAC on pin SYS_CLK.
At exit from software powerdown, the ET1011 does the
following:
■ Initializes all digital logic and state machines.
Note:
At exit from software powerdown, the H/W con-
figuration pins and the PHY address pins are
not reread and the MII registers are not reset to
their default values. These operations are only
done during reset or recovery from hardware
powerdown.
Wake-On-LAN Powerdown Mode
ACPI power consumption compliant Wake-On-LAN
mode is implemented on the ET1011 by using the IEEE
standard MII registers to put the PHY into 10Base-T or
100Base-TX modes. Clearing the advertisement of
1000Base-T (MII register address 9 bits 8, 9) and set-
ting the desired 10Base-T and 100Base-TX advertise-
ment (MII register address 4 bits 5-8) activates this
feature. This must be followed by an autonegotiation
restart via the control register (MII register address 0 bit
9).
Low-Power Energy-Detect Mode
When COMA is asserted, low-power energy-detect
(LPED) mode is enabled if LPED_EN_N is low. In this
mode, the PHY monitors the cable for energy. If energy
is detected, the MDINT_N pin is asserted. The PHY
exits from LPED mode when COMA is deasserted.
.
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ET1011.PDF ] | |
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