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Número de pieza | SC2596 | |
Descripción | Low Voltage Integrated DDR Termination Regulator | |
Fabricantes | Semtech Corporation | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de SC2596 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
No Preview Available ! POWER MANAGEMENT
Description
The SC2596 is an integrated linear DDR termination
device, which provides a complete solution for DDR
termination regulator designs; while meeting the JEDEC
requirements of SSTL-2 and SSTL-18 specifications for
DDR-SDRAM termination.
The SC2596 regulates up to +/- 2.5A for DDR-I and +/-
1.5A for DDR-II application requirements.
www.DatacVSuhTTereriset4nUret.cgroaumnlagteedwittohtsrahcokotththeroVuREgFhvoplrtoatgeectoiovne.r the entire
SC2596
Low Voltage Integrated DDR
Termination Regulator
Features
Sourcing or sinking 2.5A for DDR-I
Sourcing or sinking 1.5A for DDR-II
AVCC undervoltage lockout
Reference output
Minimum number of external components
Accurate internal voltage divider
Disable function, puts device into sleep mode
Thermal shutdown
Over current protection
Available in SOIC-8 EDP package
WEEE and RoHS compliant
A VSENSE pin is incorporated to provide excellent load
regulation, along with a buffered reference voltage for
internal use.
The SC2596 also features a disable function which is to
tri-state the output during Suspend To Ram (STR) states
by pulling the EN pin low.
Applications
DDR-I and DDR-II memory termination
SSTL-2 and SSTL-3 termination
HSTL termination
PC motherboards
Graphics boards
Disk drives
CD-ROM drives
Typical Application Circuit
EN
VDDQ
AVCC
SC2596
EN
VTT
VDDQ VSENSE
PVCC
VREF
VREF
VTT
Revision: July 18, 2007
0
1
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1 page POWER MANAGEMENT
Waveforms
4.0
3.5
3.0
2.5
2.0
www.DataSheet4U.co2m 2.5 3 3.5 4 4.5 5 5.5
AVCC(V)
Maximum Sourcing Current vs AVCC.
(VDDQ=1.8V, PVCC=2.5V)
3.0
2.5
2.0
1.5
1.0
2 2.5 3 3.5 4 4.5 5 5.5
AVCC(V)
Maximum Sourcing Current vs AVCC.
(VDDQ=1.8V, PVCC=1.8V)
SC2596
4.0
3.5
3.0
2.5
2.0
2 2.5 3 3.5 4 4.5 5 5.5
AVCC(V)
Maximum Sinking Current vs AVCC.
(VDDQ=1.8V, PVCC=2.5V)
4.0
3.5
3.0
2.5
2.0
2 2.5 3 3.5 4 4.5 5 5.5
AVCC(V)
Maximum Sinking Current vs AVCC.
(VDDQ=1.8V, PVCC=1.8V)
© 2007 Semtech Corp.
5
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5 Page POWER MANAGEMENT
Application Information (Cont.)
Layout guidelines
1) The EDP SO-8 package of SC2596 can improve the
thermal impedance (θJC) significantly. A suitable thermal
pad should be add when PCB layout. Some thermal vias
are required to connect the thermal pad to the PCB
ground layer. This will improve the thermal performance.
Please refer to the recommanded landing pattern.
www.Data2Sh)eeTto4Ui.ncocmrease the noise immunity, a ceramic capacitor
of 100nF is required to decouple the VREF pin with the
shortest connection trace.
3) To reduce the noise on input power rail for standard
SSTL-2 application, a 100µF low ESR capacitor and a
1µF ceramic capacitor capacitor have to be used on the
input power rail with shortest possible connection.
4) VTT output copper plane should be as large as
possible. A 4.7uF to 10µF capacitor have to be used to
decouple the VTT pin.
5) The trace between VSENSE pin and VTT rail should be
as short as possible and put a 10nF ~100nF capacitor
close this vsense pin.
SC2596
© 2007 Semtech Corp.
11
www.semtech.com
11 Page |
Páginas | Total 13 Páginas | |
PDF Descargar | [ Datasheet SC2596.PDF ] |
Número de pieza | Descripción | Fabricantes |
SC2595 | Integrated Linear DDR Termination Regulator | Semtech Corporation |
SC2596 | Low Voltage Integrated DDR Termination Regulator | Semtech Corporation |
SC2597 | Low Voltage DDR Termination Regulator | Semtech Corporation |
SC2598 | Low Voltage DDR Termination Regulator | Semtech |
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