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PDF 10EL34 Data sheet ( Hoja de datos )
| Número de pieza | 10EL34 | |
| Descripción | MC10EL34 | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 10EL34 (archivo pdf) en la parte inferior de esta página. Total 3 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
÷ ÷ ÷2, 4, 8 Clock
Generation Chip
The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by either
a differential or single-ended ECL or, if positive power supplies are used,
PECL input signal. In addition, by using the VBB output, a sinusoidal
www.DataShesEeotC4uULrci.nceoPmcSa™n
be AC coupled into the
Data Book DL140/D). If
device (see Interfacing section of
a single-ended input is to be used,
the
the
VBB output should be connected to the CLK input and bypassed to ground
via a 0.01µF capacitor. The VBB output is designed to act as the switching
reference for the input of the EL34 under single-ended input conditions,
as a result, this pin can only source/sink up to 0.5mA of current.
The common enable (EN) is synchronous so that the internal dividers
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on
the internal clock when the device is enabled/disabled as can happen
with an asynchronous control. An internal runt pulse could lead to losing
synchronization between the internal divider stages. The internal enable
flip-flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of the
clock input.
Upon startup, the internal flip-flops will attain a random state; the
master reset (MR) input allows for the synchronization of the internal
dividers, as well as multiple EL34s in a system.
• 50ps Output-to-Output Skew
• Synchronous Enable/Disable
• Master Reset for Synchronization
• 75kΩ Internal Input Pulldown Resistors
• >1000V ESD Protection
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
VCC EN NC CLK CLK VBB MR VEE
16 15 14 13 12 11 10 9
D
QR
÷2
QR
÷4
QR
÷8
QR
12345678
Q0 Q0 VCC Q1 Q1 VCC Q2 Q2
MC10EL34
MC100EL34
16
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B-05
PIN DESCRIPTION
PIN
CLK
EN
MR
VBB
Q0
Q1
Q2
FUNCTION
Diff Clock Inputs
Sync Enable
Master Reset
Reference Output
Diff ÷2 Outputs
Diff ÷4 Outputs
Diff ÷8 Outputs
FUNCTION TABLE
CLK EN MR FUNCTION
Z L L Divide
ZZ H
L Hold Q0–3
X X H Reset Q0–3
Z = Low-to-High Transition
ZZ = High-to-Low Transition
12/93
© Motorola, Inc. 1996
3–1
REV 2
1 page | ||
| Páginas | Total 3 Páginas | |
| PDF Descargar | [ Datasheet 10EL34.PDF ] | |
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