PDF M12L32162A Data sheet ( Hoja de datos )

Número de pieza	M12L32162A
Descripción	1M x 16Bit x 2Banks Synchronous DRAM
Fabricantes	Elite Semiconductor
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No Preview Available ! ESMT Preliminary Revision History Revision 0.1 (Aug. 11 2006) - Original Revision 0.2 (Mar. 20 2007) - Add BGA package Revision 0.3 (Apr. 27 2007) - Rename BGA pin name (BA1 to NC; BA0 to BA) - Modify DC Characteristics www.DataSheet4U.com M12L32162A Elite Semiconductor Memory Technology Inc. Publication Date : Apr. 2007 Revision : 0.3 1/29 1 page ESMT Preliminary M12L32162A DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70 °C VIH(min)/VIL(max)=2.0V/0.8V) Parameter Symbol Test Condition CAS Latency Version -7 Operating Current (One Bank Active) ICC1 Burst Length = 1 tRC ≥ tRC (min), tCC ≥ tCC (min), IOL= 0mA 100 Precharge Standby www.DataSheCmeuto4rdUree.cnotmin power-down ICC2P ICC2PS CKE ≤ VIL(max), tCC =15ns CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞ 2 2 Precharge Standby Current in non power-down mode ICC2N ICC2NS CKE ≥ VIH(min), CS ≥ VIH(min), tCC =15ns Input signals are changed one time during 30ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable Active Standby Current in power-down mode ICC3P ICC3PS CKE ≤ VIL(max), tCC =15ns CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞ Active Standby Current in non power-down mode (One Bank Active) ICC3N ICC3NS CKE ≥ VIH(min), CS ≥ VIH(min), tCC=15ns Input signals are changed one time during 30ns CKE ≥ VIH (min), CLK ≤ VIL(max), tCC= ∞ Input signals are stable Operating Current (Burst Mode) IOL= 0Ma, Page Burst ICC4 All Band Activated, tCCD = tCCD (min) 3 2 Refresh Current ICC5 tRC ≥ tRC(min) Self Refresh Current ICC6 CKE ≤ 0.2V Note: 1.Measured with outputs open. Addresses are changed only one time during tCC(min). 2.Refresh period is 64ms. Addresses are changed only one time during tCC(min). 25 15 10 10 25 15 120 120 120 1 Unit Note mA 1 mA mA mA mA mA mA mA 1 mA 2 mA Elite Semiconductor Memory Technology Inc. Publication Date : Apr. 2007 Revision : 0.3 5/29 5 Page ESMT Preliminary M12L32162A Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency=3, Burst Length=1 CLOCK CKE www.DataSheet4UC.cSom RAS CAS ADDR BA tCH 0 123 45 tCC Note1 tCL tRAS tRC tSH tRCD tSS tSH Ra tSS Note2 BS tSH tSS Ca Note2,3 BS 6 7 8 9 10 11 12 13 14 15 16 17 18 19 HIGH tSH tSS tCCD tRP tSS Cb tSH Note2,3 BS Cc Note2,3 BS Note4 BS Rb Note2 BS A10/AP DQ WE DQM Ra Note 3 tRAC tSAC tSLZ Note 3 Note 3 *Note4 Qa tOH tSH Db tSH tSS tSS tSS tSH Rb Qc Row Active Read Write Read Precharge Row Active :Don't Care Elite Semiconductor Memory Technology Inc. Publication Date : Apr. 2007 Revision : 0.3 11/29 11 Page

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Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
M12L32162A	1M x 16Bit x 2Banks Synchronous DRAM	Elite Semiconductor

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