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PDF P521-38 Data sheet ( Hoja de datos )
| Número de pieza | P521-38 | |
| Descripción | Low Phase Noise PECL VCXO | |
| Fabricantes | PhaseLink Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de P521-38 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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Preliminary P521-38
Low Phase Noise PECL VCXO (65MHz to 130MHz)
FEATURES
• 65MHz to 130MHz Fundamental Mode Crystal.
• Output range: 65MHz – 130MHz.
• Complementary PECL outputs.
• Selectable OE Logic (enable high or enable low).
• Integrated variable capacitors.
• High pull linearity: < 5%.
www.DataShe•et4U.+c/o-m125 ppm pull range
• Supports 2.5V or 3.3V-Power Supply.
• Available in die form.
• Thickness 10 mil.
DESCRIPTIONS
P521-38 is a VCXO IC specifically designed to pull
high frequency fundamental crystals. Its internal
varicaps allow an on chip frequency pulling,
controlled by the VCON input. The chip provides a
low phase noise, low jitter PECL differential clock
output.
BLOCK DIAGRAM
VCON Oscillator
Amplifier
X+
w/
integrated
varicaps
X-
OE
Q
Q
P521-38
DIE CONFIGURATION
57.5 mil
GNDOSC 18
17 16
VCON 19
XIN 20
XOUT 21
OE 22
1
2
(1460,1435)
15 14 13
12
11
34
10
9
8
7
56
VDDANA
VDDBUF
VDDBUF
PECLBAR
PECL
GNDBUF
Y (0,0)
X
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
56.5 x 57.5 mil
GND
80 micron x 80 micron
10 mil
OUTPUT ENABLE LOGIC SELECTION
OESEL
(Pad #14)
OECTRL
(Pad #22)
State
0 (Default)
0 (Default) Output enabled
1 Tri-state
1
0 Tri-state
1 (Default) Output enabled
Pad #14, 22: Bond to GND to set to “0”, bond to VDD to set to “1”
No connection results to “default” setting through internal pull-up/-down.
Pad #22: Logical states defined by PECL VIH and VIL levels.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 3/02/04 Page 1
1 page  
Preliminary P521-38
Low Phase Noise PECL VCXO (65MHz to 130MHz)
7. PECL Electrical Characteristics
PARAMETERS
Output High Voltage
Output Low Voltage
SYMBOL
VOH
VOL
CONDITIONS
RL = 50 Ω to (VDD – 2V)
(see figure)
8. PECL Switching Characteristics
www.DataSheet4U.com
PARAMETERS
SYMBOL
CONDITIONS
Clock Rise Time
Clock Fall Time
tr @20/80% - PECL
tf @80/20% - PECL
MIN.
VDD – 1.025
MAX.
VDD – 1.620
UNITS
V
V
MIN. TYP. MAX. UNITS
0.6 1.5
0.5 1.5
ns
ns
PECL Levels Test Circuit
OUT
VDD
50Ω 2.0V
PECL Output Skew
OUT
50%
OUT
50Ω
OUT
80%
50%
20%
OUT
tR
OUT
tSKEW
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
tF
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 3/02/04 Page 5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet P521-38.PDF ] | |
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