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Número de pieza | P521-39 | |
Descripción | Low Phase Noise PECL VCXO | |
Fabricantes | PhaseLink Corporation | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de P521-39 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
No Preview Available ! Preliminary P521-39
Low Phase Noise LVDS VCXO (65MHz to 130MHz)
FEATURES
• 65MHz to 130MHz Fundamental Mode Crystal.
• Output range: 65MHz – 130MHz.
• Complementary LVDS outputs.
• Selectable OE Logic (enable high or enable low).
• Integrated variable capacitors.
• High pull linearity: < 5%.
www.DataShe•et4U.+c/o-m125 ppm pull range
• Supports 2.5V or 3.3V-Power Supply.
• Available in die form.
• Thickness 10 mil.
DESCRIPTIONS
P521-39 is a VCXO IC specifically designed to pull
high frequency fundamental crystals. Its internal
varicaps allow an on chip frequency pulling,
controlled by the VCON input. The chip provides a
low phase noise, low jitter LVDS differential clock
output.
BLOCK DIAGRAM
VCON Oscillator
Amplifier
X+
w/
integrated
varicaps
X-
OE
Q
Q
P521-39
DIE CONFIGURATION
57.5 mil
GNDOSC 18
17 16
VCON 19
XIN 20
XOUT 21
OE 22
1
2
(1460,1435)
15 14 13
12
11
34
10
9
8
7
56
VDDANA
VDDBUF
VDDBUF
PECLBAR
PECL
GNDBUF
Y (0,0)
X
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
56.5 x 57.5 mil
GND
80 micron x 80 micron
10 mil
OUTPUT ENABLE LOGIC SELECTION
OESEL
(Pad #14)
OECTRL
(Pad #22)
State
0 (Default)
0 Tri-state
1 (Default) Output enabled
1
0 (Default) Output enabled
1 Tri-state
Pad #14, 22: Bond to GND to set to “0”, bond to VDD to set to “1”
No connection results to “default” setting through internal pull-up/-down.
Pad #22: Logical states defined by CMOS VIH and VIL levels.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 3/02/04 Page 1
1 page Preliminary P521-39
Low Phase Noise LVDS VCXO (65MHz to 130MHz)
7. LVDS Electrical Characteristics
PARAMETERS
SYMBOL
Output Differential Voltage
VDD Magnitude Change
Output High Voltage
Output Low Voltage
www.DataSheetO4Uff.sceotmVoltage
Offset Magnitude Change
Power-off Leakage
Output Short Circuit Current
VOD
∆VOD
VOH
VOL
VOS
∆VOS
IOXD
IOSD
CONDITIONS
RL = 100 Ω
(see figure)
Vout = VDD or GND
VDD = 0V
MIN.
247
-50
0.9
1.125
0
TYP.
355
1.4
1.1
1.2
3
±1
-5.7
MAX.
454
50
1.6
1.375
25
±10
-8
UNITS
mV
mV
V
V
V
mV
uA
mA
8. LVDS Switching Characteristics
PARAMETERS
Differential Clock Rise Time
Differential Clock Fall Time
SYMBOL
tr
tf
CONDITIONS
RL = 100 Ω
CL = 10 pF
(see figure)
MIN.
0.2
0.2
TYP.
0.7
0.7
MAX.
1.0
1.0
UNITS
ns
ns
LVDS Levels Test Circuit
OUT
OUT
VOD
50Ω
VOS
50Ω
LVDS Switching Test Circuit
OUT
CL = 10pF
VDIFF
OUT
CL = 10pF
RL = 100Ω
LVDS Transistion Time Waveform
OUT
OUT
0V (Differential)
VDIFF
0V
20%
80%
tR
80%
20%
tF
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 3/02/04 Page 5
5 Page |
Páginas | Total 6 Páginas | |
PDF Descargar | [ Datasheet P521-39.PDF ] |
Número de pieza | Descripción | Fabricantes |
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P521-39 | Low Phase Noise PECL VCXO | PhaseLink Corporation |
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