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PDF PC33880 Data sheet ( Hoja de datos )
| Número de pieza | PC33880 | |
| Descripción | Configurable Octal Serial Switch | |
| Fabricantes | Motorola Semiconductor | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
Configurable Octal Serial Switch
with Serial Peripheral Interface I/O
The 33880 device is an eight output hardware configurable high side/low
side switch with 8-bit serial input control. Two of the outputs may be controlled
directly via microprocessor for PWM applications. The 33880 incorporates
SMARTMOS™ technology, with CMOS logic, bipolar/MOS analog circuitry,
and DMOS power MOSFETs. The 33880 controls various inductive or
www.DataSheeitn4cUa.cnodmescent loads by directly interfacing with a micro controller. The circuit’s
innovative monitoring and protection features include: very low standby
currents; cascade fault reporting; internal +40 V clamp voltage for low side
configuration; -20 V high side configuration; output specific diagnostics; and
independent shutdown of output.
Features
• Designed to operate 5.5 V < VPWR < 24.5 V
• 8-Bit SPI for Control and Fault Reporting, 3.3 V/5.0 V Compatible
• Outputs are current limited (0.8 A to 2 A) to Drive Incandescent Lamps
• Output voltage Clamp, +45 V (low side) and -20 V (high side) During
Inductive Switching
• Internal Reverse Battery Protection on VPWR
• Loss of Ground or Supply Will Not Energize Loads or Damage IC
• Maximum 5 µA IPWR Standby Current at 13.0 V VPWR
• RDS(ON) of 0.55Ω at 25°C Typical
• Short Circuit Detect and Current Limit with Automatic Retry
• Independent Over Temperature Protection
Document order number: MC33880/D
Rev 1, 09/2002
33880
CONFIGURABLE OCTAL SERIAL
SWITCH WITH SERIAL
PERIPHERAL INTERFACE
Package Options
28-Lead SOIC
Case751F
32-Lead Fine
Pitch SOIC
CASE 1324
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
PC33880DW
-40°C to 125°C 28 Ld SOIC
PC33880DWB -40°C to 125°C 32 Ld SOIC
MCU
A0
MOSI
SCLK
CS
MISO
PWM1
PWM2
33880 Simplified Application Schematic
+5.0V
VPWR
VBAT
33880
VPWR
VDD
EN
DI
D1
D2
D3
D4
S1
SCLK
S2
CS S3
DO S4
M
IN5 D5
IN6 D6
D7
D8
GND
S5
S6
S7
S8
High Side Drive
H-Bridge Configuration
VBAT VBAT
Low Side Drive
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Motorola, Inc. 2002
1 page  
www.DataSheet4U.com
GND
VDD
S8
S8
D8
S2
D2
GND
GND
S1
D1
D6
S6
IN6
EN
SCLK
1 32
2 31
3 30
4 29
5 28
6 27
7 26
8 25
9 24
10 23
11 22
12 21
13 20
14 19
15 18
16 17
32 Lead SOIC
DO
VPWR
S7
S7
D7
S4
D4
GND
GND
S3
D3
D5
S5
IN5
CS
DI
PIN FUNCTION DESCRIPTON 32 SOIC
SOIC-32
PIN
PIN NAME
1
GND
Digital ground.
DESCRIPTION
2 VDD Logic supply voltage. Logic supply must be switched off for low current mode (VDD below 3.9 V).
3 S8 Output eight MOSFET source pin.
4 S8 Output eight MOSFET source pin.
5 D8 Output eight MOSFETdrain pin.
6 S2 Output two MOSFET source pin.
7 D2 Output two MOSFET drain pin.
8
GND
Thermal enhanced ground pin.
9
GND
Thermal enhanced ground pin.
10 S1 Output one MOSFET source pin.
11 D1 Output one MOSFET drain pin.
12 D6 Output six MOSFETdrain pin.
13 S6 Output six MOSFET source pin.
14 IN6 PWM direct control input pin for output 6. IN6 is “AND” with SPI bit.
15 EN Enable input. Allows control of outputs. Active high.
16
SCLK
SPI control clock input pin.
17 DI SPI control data input pin from MCU to the 33880. Logic 1 activates output.
18 CS SPI control chip select input pin from MCU to the 33880. Logic 0 allows data to be transferred in.
19 IN5 PWM direct control input pin for output 5. IN5 is “AND” with SPI bit.
20 S5 Output five MOSFET source pin.
21 D5 Output five MOSFET drain pin.
22 D3 Output three MOSFET drain pin.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33880
5
5 Page 
DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions of 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 125°C, unless otherwise
noted. Typical values, where applicable, reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C
Characteristic
Digital Interface Timing
Symbol
Min
Typ
Max
Units
Recommended Frequency of SPI Operation
— 4.0 6.0
MHz
Required Low State Duration on VDD for Reset (VDD ≤ 0.2 V) (Note16)
tRESET
—
4.0
10
µs
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
tLEAD
100
—
—
ns
www.DataSheet4UF.caollming Edge of SCLK to Rising Edge of CS (Required Setup Time)
tLAG 50 —
—
ns
DI to Falling Edge of SCLK (Required Setup Time)
tDI(su)
16
—
—
ns
Falling Edge of SCLK to DI (Required Hold Time)
tDI(HOLD)
20
—
—
ns
DI, CS, SCLK Signal Rise Time (Note17)
tr(DI)
—
5
—
ns
DI, CS, SCLK Signal Fall Time (Note17)
tf(DI)
—
5
—
ns
Time from Falling Edge of CS to DO Low Impedance (Note18)
tDO(EN)
—
—
55
ns
Time from Rising Edge of CS to DO High Impedance (Note19)
tDO(DIS)
—
—
55
ns
Time from Rising Edge of SCLK to DO Data Valid (Note20)
tVALID
—
25
55
ns
Notes:
16. This parameter is guaranteed by design, but not production tested.
17. Rise and Fall time of incoming DI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
18. Time required for output status data to be available for use at DO pin.
19. Time required for output status data to be terminated at DO pin
20. Time required to obtain valid data out from DO following the rise of SCLK.
CS
SCLK
DI
DO
0.2 VDD
tlead
0.7 VDD
0.2 VDD
tDI(su) tDI(hold)
0.7 VDD
0.2 VDD
MSB in
tDO(en)
0.7 VDD
0.2 VDD
MSB out
tvalid
Figure 2. SPI Timing Diagram
tlag
tDO(dis)
LSB out
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33880
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet PC33880.PDF ] | |
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