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PDF 80C196NU Data sheet ( Hoja de datos )
| Número de pieza | 80C196NU | |
| Descripción | COMMERCIAL CHMOS MICROCONTROLLER | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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PRELIMINARY
8XC196NU COMMERCIAL
CHMOS 16-BIT MICROCONTROLLER
s 50 MHz Operation†
s 1 Mbyte of Linear Address Space
s Optional 48 Kbytes of ROM
s 1 Kbyte of Register RAM
s Register-register Architecture
s Footprint and Functionally Compatible
Upgrade for the 8XC196NP
s 32 I/O Port Pins
s 16 Prioritized Interrupt Sources
s 4 External Interrupt Pins and NMI Pin
s 2 Flexible 16-bit Timer/Counters with
www.DataSheet4U.cQomuadrature Counting Capability
s 3 Pulse-width Modulator (PWM)
Outputs with High Drive Capability
s Full-duplex Serial Port with Dedicated
Baud-rate Generator
s Peripheral Transaction Server
† 40 MHz standard; 50 MHz is Speed Premium
s Chip-select Unit
— 6 Chip-select Pins
— Dynamic Demultiplexed/Multiplexed
Address/Data Bus for Each
Chip Select
— Programmable Wait States
(0–3) for Each Chip Select
— Programmable Bus Width
(8- or 16-bit) for Each Chip Select
— Programmable Address Range for
Each Chip Select
s Event Processor Array (EPA) with
4 High-speed Capture/Compare
Channels
s Multiply and Accumulate Executes in
640 ns Using the 32-bit Hardware
Accumulator
s 960 ns 32/16 Unsigned Division
s 100-pin SQFP or 100-pin QFP Package
s Complete System Development
Support
s High-speed CHMOS Technology
The 8XC196NU is a member of Intel’s 16-bit MCS® 96 microcontroller family. The device features 1 Mbyte of
linear address space, a demultiplexed bus, and a chip-select unit. The external bus can dynamically switch
between multiplexed and demultiplexed operation.
COPYRIGHT © INTEL CORPORATION, 1997
February 1997
Order Number: 272644-004
1 page  
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
1.0 PRODUCT OVERVIEW
The 8XC196NU is a member of Intel’s 16-bit MCS® 96 microcontroller family. The device features 1 Mbyte of
linear address space, a demultiplexed bus, and a chip-select unit. The external bus can dynamically switch
between multiplexed and demultiplexed operation.
CPU
1000
Byte
Register
File
www.DataSheet4U.com
24 Bytes
CPU SFRs
Timer 1
Timer 2
RALU
16
Interrupt
Controller
48 Kbytes
ROM
(optional)
Microcode
Engine
Peripheral
Transaction
Server
8
16
Event
Processor
Array
Serial
Port
Memory Controller
with
Chip Select
Queue
Chip Select
CS5:0#
Control
Signals
A19:16/
EPORT3:0
Baud
Rate
Gen
Pulse
Width
Modulator
A15:0
AD15:0
Port 1
Port 2
Port Port
34
Port 1/
EPA3:0,
Timer 1,
Timer 2
Port 2/
Hold Control,
SIO,
EXTINT1:0
Port 3/ Port 4/
EXTINT3:2 PWM2:0
Figure 1. 8XC196NU Block Diagram
A2822-02
PRELIMINARY
1
5 Page 
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 4. 80C196NU 100-pin QFP Pin Assignment
Pin
Name
Pin
Name
Pin
Name
Pin Name
1 AD0
26 EXTINT2/P3.6
51 HOLD#/P2.5
76 RD#
2 NC
27 NC
52 HLDA#/P2.6
77 WR#/WRL#
3 RESET#
4 NMI
28 EXTINT3/P3.7
29 EPA0/P1.0
53 VCC
54 CLKOUT/P2.7
78 EPORT.3/A19
79 EPORT.2/A18
5 NC
6 A0
7 A1
30 VCC
31 EPA1/P1.1
32 EPA2/P1.2
55 VSS
56 XTAL2
57 XTAL1
80 VSS
81 VCC
82 EPORT.1/A17
8 VCC
9 VSS
www.DataSheet41U0.comA2
11 A3
12 A4
33 EPA3/P1.3
34 T1CLK/P1.4
35 T1DIR/P1.5
36 VCC
37 T2CLK/P1.6
58 VSS
59 A15
60 A14
61 A13
62 A12
83 EPORT.0/A16
84 AD15
85 AD14
86 AD13
87 AD12
13 A5
14 A6
38 VSS
39 T2DIR/P1.7
63 A11
64 A10
88 AD11
89 AD10
15 A7
40 PWM0/P4.0
65 A9
90 AD9
16 VCC
17 VSS
18 PLLEN1
19 CS0#/P3.0
20 CS1#/P3.1
21 CS2#/P3.2
41 PWM1/P4.1
42 PWM2/P4.2
43 P4.3
44 VCC
45 VSS
46 TXD/P2.0
66 A8
67 VSS
68 VCC
69 PLLEN2
70 ONCE
71 RPD
91 VSS
92 AD8
93 VCC
94 AD7
95 AD6
96 AD5
22 CS3#/P3.3
47 RXD/P2.1
72 READY
97 AD4
23 VSS
24 CS4#/P3.4
48 EXTINT0/P2.2
49 BREQ#/P2.3
73 INST
74 ALE
98 AD3
99 AD2
25 CS5#/P3.5
50 EXTINT1/P2.4
75 BHE#/WRH#
100 AD1
NOTE:
To be compatible with future proliferations, tie the NC (no connect) pin as follows:
Pin 2 = VSS
Pin 5 = EA# on products with internal memory (VCC = internal memory, VSS = external memory)
Pin 27 = VCC
PRELIMINARY
7
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