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PDF S80C196KB16 Datasheet ( Hoja de datos )

Número de pieza S80C196KB16
Descripción COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER
Fabricantes Intel Corporation 
Logotipo Intel Corporation Logotipo
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S80C196KB16 datasheet

1 Page

S80C196KB16 pdf
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8XC196KB 8XC196KB16
NOTE
N C means No Connect (do not connect these pins)
270909 – 4
Figure 4 80-Pin QFP Package
NOTE
The above pin out diagram applies to the OTP (87C196KB) device The OTP device uses all of the programming pins shown
above The ROM (83C196KB) device only uses programming pins AINC PALE PMODE n and PROG The ROMless
(80C196KB) doesn’t use any of the programming pins
5

5 Page

S80C196KB16 arduino
8XC196KB 8XC196KB16
AC CHARACTERISTICS (Continued)
Test Conditions Capacitive load on all pins e 100 pF Rise and fall times e 10 ns FOSC e 12 16 MHz
The 87C196KB will meet these specifications
Symbol
Description
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FXTAL
FXTAL
TOSC
TOSC
TXHCH
TCLCL
TCHCL
TCLLH
TLLCH
TLHLH
TLHLL
TAVLL
TLLAX
TLLRL
TRLCL
TRLRH
TRHLH
TRLAZ
TLLWL
TCLWL
TQVWH
TCHWH
TWLWH
TWHQX
TWHLH
TWHBX
TRHBX
TWHAX
TRHAX
Frequency on XTAL1 12 MHz
Frequency on XTAL1 16 MHz
1 FXTAL 12 MHz
1 FXTAL 16 MHz
XTAL1 High to CLKOUT High or Low
CLKOUT Cycle Time
CLKOUT High Period
CLKOUT Falling Edge to ALE Rising
ALE Falling Edge to CLKOUT Rising
ALE Cycle Time
ALE High Period
Address Setup to ALE Falling Edge
Address Hold after ALE Falling Edge
ALE Falling Edge to RD Falling Edge
RD Low to CLKOUT Falling Edge
RD Low Period
RD Rising Edge to ALE Rising Edge
RD Low to Address Float
ALE Falling Edge to WR Falling Edge
CLKOUT Low to WR Falling Edge
Data Stable to WR Rising Edge
CLKOUT High to WR Rising Edge
WR Low Period
Data Hold after WR Rising Edge
WR Rising Edge to ALE Rising Edge
BHE INST HOLD after WR Rising Edge
BHE INST HOLD after RD Rising Edge
AD8–15 hold after WR Rising Edge
AD8–15 hold after RD Rising Edge
Min Max
3 5 12 0
3 5 16 0
83 3
286
62 5
286
a20
a110
2 TOSC
TOSC b 10 TOSCa10
b10
a10
b15
a15
4 TOSC
TOSC b 10 TOSCa10
TOSC b 20
TOSC b 40
TOSC b 35
a4 a25
TOSCb5
TOSC
TOSC a 25
TOSC a 25
a5
TOSC b 10
0
a25
TOSC b 23
b5
a15
TOSC b 15
TOSC b 15
TOSC b 15
TOSC b 15
TOSC b 10
TOSC b 30
TOSC b 25
TOSC a 5
TOSC a 10
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
(Note 2)
(Note 2)
(Note 3)
(Note 3)
(Note 1)
(Note 3)
(Note 3)
(Note 1)
NOTES
1 Assuming back-to-back bus cycles
2 Testing performed at 3 5 MHz however the device is static by design and will typically operate below 1 Hz
3 When using wait states all 2 TOSCa n where n e number of wait states
11

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