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PDF TC1302B Data sheet ( Hoja de datos )
| Número de pieza | TC1302B | |
| Descripción | LOW QUIESCENT CURRENT DUAL OUTPUT LDO | |
| Fabricantes | Microchip Technology | |
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TC1302A/B
Low Quiescent Current Dual Output LDO
Features
• Dual Output LDO:
- VOUT1 = 1.5V to 3.3V @ 300 mA
- VOUT2 = 1.5V to 3.3V @ 150 mA
• Output Voltage (See Table 8-1)
www.DataSheet4U.com• Low Dropout Voltage:
- VOUT1 = 104 mV @ 300 mA Typical
- VOUT2 = 150 mV @ 150 mA Typical
• Low Supply Current: 116 µA Typical
TC1302A/B with both output voltages available
• Reference Bypass Input for Low-Noise Operation
• Both Output Voltages Stable with a Minimum of
1 µF Ceramic Output Capacitor
• Separate VOUT1 and VOUT2 SHDN pins
(TC1302B)
• Power-Saving Shutdown Mode of Operation
• Wake-up from SHDN: 5.3 µs. Typical
• Small 8-pin DFN or MSOP Package Options
• Operating Junction Temperature Range:
- -40°C to +125°C
• Overtemperature and Overcurrent Protection
Applications
• Cellular/GSM/PHS Phones
• Battery-Operated Systems
• Hand-Held Medical Instruments
• Portable Computers/PDAs
• Linear Post-Regulators for SMPS
• Pagers
Related Literature
• AN765, “Using Microchip’s Micropower LDOs”,
DS00765, Microchip Technology Inc., 2002
• AN766, “Pin-Compatible CMOS Upgrades to
BiPolar LDOs”, DS00766,
Microchip Technology Inc., 2002
• AN792, “A Method to Determine How Much
Power a SOT23 Can Dissipate in an Application”,
DS00792, Microchip Technology Inc., 2001
Description
The TC1302A/B combines two Low Dropout (LDO)
regulators into a single 8-pin MSOP or DFN package.
Both regulator outputs feature low dropout voltage,
104 mV @ 300 mA for VOUT1, 150 mV @ 150 mA for
VOUT2, low quiescent current consumption, 58 µA each
and a typical regulation accuracy of 0.5%. Several
fixed-output voltage combinations are available. A
reference bypass pin is available to further reduce
output noise and improve the power supply rejection
ratio of both LDOs.
The TC1302A/B is stable over all line and load
conditions, with a minimum of 1 µF of ceramic output
capacitance, and utilizes a unique compensation
scheme to provide fast dynamic response to sudden
line voltage and load current changes.
Additional features include an overcurrent limit and
overtemperature protection that combine to provide a
robust design for all load fault conditions.
Package Types
8-Pin DFN/MSOP
DFN8
TC1302A
MSOP8
NC 1
VOUT1 2
GND 3
Bypass 4
8 NC
NC 1
7 VIN
VOUT1 2
6 VOUT2 GND 3
5 SHDN2 Bypass 4
8 NC
7 VIN
6 VOUT2
5 SHDN2
DFN8
TC1302B
MSOP8
NC 1
VOUT1 2
GND 3
Bypass 4
8 SHDN1 NC 1
7 VIN
6 VOUT2
VOUT1 2
GND 3
5 SHDN2 Bypass 4
8 SHDN1
7 VIN
6 VOUT2
5 SHDN2
© 2005 Microchip Technology Inc.
DS21333B-page 1
1 page  
TC1302A/B
2.0 TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, VIN = VR +1V, IOUT1 = IOUT2 = 100 µA, CIN = 4.7 µF, COUT1 = COUT2 = 1 µF (X5R or X7R),
CBYPASS = 0 pF, SHDN1 = SHDN2 > VIH, TA = +25°C.
www.DataSheet4U.com
350
300
250
TC1302B
TJ = +25°C
IOUT1 = IOUT2 = 0 µA
VOUT1 Active
200
150
VOUT2 Active
VOUT2 SHDN
100
50
0
2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6.0
Input Voltage (V)
FIGURE 2-1:
Voltage.
Quiescent Current vs. Input
3.00
2.90
2.80
VOUT1
TJ = +25°C
IOUT1 = 100 mA
IOUT2 = 50 mA
2.70
VOUT2
2.60
2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6
Input Voltage (V)
FIGURE 2-4:
Voltage.
Output Voltage vs. Input
1.8
1.7
1.6
1.5 ON
1.4
1.3
1.2
1.1 OFF
1.0
0.9
0.8
2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6
Input Voltage (V)
FIGURE 2-2:
SHDN Voltage Threshold
vs. Input Voltage.
2.90
2.85
VOUT1
2.80
2.75
2.70
2.65
VOUT2
2.60
2.55
2.50
TJ = +25°C
IOUT1 = 300 mA
IOUT2 = 100 mA
2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6
Input Voltage (V)
FIGURE 2-5:
Voltage.
Output Voltage vs. Input
140
130
120
110
TC1302B
VOUT2 Active
VIN = 4.2V
IOUT1 = IOUT2 = 0 µA
VOUT1 Active
100
90
VOUT2 SHDN
80
70
60
50
40
-40 -25 -10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
FIGURE 2-3:
Quiescent Current vs.
Junction Temperature.
140.0
120.0
100.0
80.0
60.0
VR1 = 2.8V
VR2 = 2.6V
IOUT2 = 100 µA
TJ = +125°C
TJ = +25°C
TJ = - 40°C
40.0
20.0
0.0
0
50 100 150 200 250
IOUT1 (mA)
300
FIGURE 2-6:
Dropout Voltage vs. Output
Current (VOUT1).
© 2005 Microchip Technology Inc.
DS21333B-page 5
5 Page 
TC1302A/B
4.0 TC1302B PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 4-1.
TABLE 4-1:
Pin No.
1
2
3
4
www.DataSheet4U.com
5
6
7
8
TC1302B PIN FUNCTION TABLE
Name
Function
NC
VOUT1
GND
Bypass
SHDN2
VOUT2
VIN
SHDN1
No connect.
Regulated output voltage #1, capable of 300 mA.
Circuit ground pin.
Internal reference bypass pin. A 10 nF external capacitor can be used to further reduce
output noise and improve PSRR performance.
Output #2 shutdown control input.
Regulated output voltage #2, capable of 150 mA.
Unregulated Input voltage pin.
Output #1 shutdown control input.
4.1 Regulated Output Voltage #1
(VOUT1)
Connect VOUT1 to the positive side of the VOUT1
capacitor and load. Capable of 300 mA maximum
output current. For the TC1302B, VOUT1 can be turned
ON and OFF using the SHDN1 input pin.
4.5 Regulated Output Voltage #2
(VOUT2)
Connect VOUT2 to the positive side of the VOUT2
capacitor and load. This pin is capable of a maximum
output current of 150 mA. VOUT2 can be turned ON and
OFF using SHDN2.
4.2 Circuit Ground Pin (GND)
Connect GND to the negative side of the input and
output capacitor. Only the LDO internal circuitry bias
current flows out of this pin (200 µA maximum).
4.3 Reference Bypass Input
By connecting an external 10 nF capacitor (typical) to
the bypass input, both outputs (VOUT1 and VOUT2) will
have less noise and improved Power Supply Ripple
Rejection (PSRR) performance. The LDO output
voltage startup time will increase with the addition of an
external bypass capacitor. By leaving this pin
unconnected, the startup time will be minimized.
4.4 Output Voltage #2 Shutdown
(SHDN2)
ON/OFF control is performed by connecting SHDN2 to
its proper level. When this pin is connected to a voltage
less than 15% of VIN, VOUT2 will be OFF. If this pin is
connected to a voltage that is greater than 45% of VIN,
VOUT2 will be turned ON.
4.6 Unregulated Input Voltage Pin
(VIN)
Connect the unregulated input voltage source to VIN. If
the input voltage source is located more than several
inches away, or is a battery, a typical minimum input
capacitance of 1 µF and 4.7 µF is recommended.
4.7 Output Voltage #1 Shutdown
(SHDN1)
ON/OFF control is performed by connecting SNDN1 to
its proper level. When this pin is connected to a voltage
less than 15% of VIN, VOUT1 will be OFF. If this pin is
connected to a voltage that is greater than 45% of VIN,
VOUT1 will be turned ON.
© 2005 Microchip Technology Inc.
DS21333B-page 11
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet TC1302B.PDF ] | |
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