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PDF 29F400T Data sheet ( Hoja de datos )
| Número de pieza | 29F400T | |
| Descripción | M29F400T | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M29F400T
M29F400B
4 Mbit (512Kb x8 or 256Kb x16, Boot Block)
Single Supply Flash Memory
M29F400T and M29F400B are replaced
respectively by the M29F400BT and
M29F400BB
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5V±10% SUPPLY VOLTAGE for PROGRAM,
ERASE and READ OPERATIONS
FAST ACCESS TIME: 55ns
FAST PROGRAMMING TIME
– 10µs by Byte / 16µs by Word typical
PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Byte-by-Byte or Word-by-Word
– Status Register bits and Ready/Busy Output
MEMORY BLOCKS
– Boot Block (Top or Bottom location)
– Parameter and Main blocks
BLOCK, MULTI-BLOCK and CHIP ERASE
MULTI-BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
LOW POWER CONSUMPTION
– Stand-by and Automatic Stand-by
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Device Code, M29F400T: 00D5h
– Device Code, M29F400B: 00D6h
DESCRIPTION
The M29F400 is a non-volatile memory that may
be erased electrically at the block or chip level and
programmed in-system on a Byte-by-Byte or Word-
by-Word basis using only a single 5V VCC supply.
For Program and Erase operations the necessary
high voltages are generated internally. The device
can also be programmed in standard program-
mers.
The array matrix organisation allows each block to
be erased and reprogrammed without affecting
other blocks. Blocks can be protected against pro-
NOT FOR NEW DESIGN
TSOP48 (N)
12 x 20 mm
44
1
SO44 (M)
Figure 1. Logic Diagram
VCC
18
A0-A17
15
DQ0-DQ14
W DQ15A–1
E
M29F400T
M29F400B
BYTE
G RB
RP
VSS
AI01726B
November 1999
This is information on a product stil l in production but not recommended for new designs.
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1 page  
M29F400T, M29F400B
Table 3A. M29F400T Block Address Table
Address Range (x8) Address Range (x16) A17 A16 A15 A14 A13 A12
00000h-0FFFFh
00000h-07FFFh
0 0 0XXX
10000h-1FFFFh
08000h-0FFFFh
0 0 1XXX
20000h-2FFFFh
10000h-17FFFh
0 1 0XXX
30000h-3FFFFh
18000h-1FFFFh
0 1 1XXX
40000h-4FFFFh
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50000h-5FFFFh
20000h-27FFFh
28000h-2FFFFh
1 0 0XXX
1 0 1XXX
60000h-6FFFFh
30000h-37FFFh
1 1 0XXX
70000h-77FFFh
38000h-3BFFFh 1 1 1 0 X X
78000h-79FFFh 3C000h-3CFFFh 1 1 1 1 0 0
7A000h-7BFFFh 3D000h-3DFFFh 1 1 1 1 0 1
7C000h-7FFFFh 3E000h-3FFFFh 1 1 1 1 1 X
Table 3B. M29F400B Block Address Table
Address Range (x8) Address Range (x16) A17 A16 A15 A14 A13 A12
00000h-03FFFh
00000h-01FFFh 0 0 0 0 0 X
04000h-05FFFh
02000h-02FFFh 0 0 0 0 1 0
06000h-07FFFh
03000h-03FFFh 0 0 0 0 1 1
08000h-0FFFFh
04000h-07FFFh 0 0 0 1 X X
10000h-1FFFFh
08000h-0FFFFh
0 0 1XXX
20000h-2FFFFh
10000h-17FFFh
0 1 0XXX
30000h-3FFFFh
18000h-1FFFFh
0 1 1XXX
40000h-4FFFFh
20000h-27FFFh
1 0 0XXX
50000h-5FFFFh
28000h-2FFFFh
1 0 1XXX
60000h-6FFFFh
30000h-37FFFh
1 1 0XXX
70000h-7FFFFh
38000h-3FFFFh
1 1 1XXX
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5 Page 
M29F400T, M29F400B
Table 9. Status Register Bits
DQ Name Logic Level
Definition
Note
7
Data
Polling
’1’
Erase Complete or erase
block in Erase Suspend
’0’ Erase On-going
Indicates the P/E.C. status, check during
Program or Erase, and on completion
Program Complete or data
before checking bits DQ5 for Program or
Erase Success.
DQ of non erase block during
Erase Suspend
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6
Toggle Bit
DQ Program On-going
’-1-0-1-0-1-0-1-’ Erase or Program On-going
DQ Program Complete
Erase Complete or Erase
’-1-1-1-1-1-1-1-’ Suspend on currently
addressed block
Successive reads output complementary
data on DQ6 while Programming or Erase
operations are on-going. DQ6 remains at
constant level when P/E.C. operations are
completed or Erase Suspend is
acknowledged.
5 Error Bit
’1’ Program or Erase Error This bit is set to ’1’ in the case of
’0’
Program or Erase On-going
Programming or Erase failure.
4 Reserved
3
Erase
Time Bit
P/E.C. Erase operation has started. Only
’1’ Erase Timeout Period Expired possible command entry is Erase Suspend
(ES).
’0’
Erase Timeout Period
On-going
An additional block to be erased in parallel
can be entered to the P/E.C.
Chip Erase, Erase or Erase
Suspend on the currently
’-1-0-1-0-1-0-1-’
addressed block.
Erase Error due to the
2 Toggle Bit
currently addressed block
(when DQ5 = ’1’).
Indicates the erase status and allows to
identify the erased block
Program on-going, Erase
1 on-going on another block or
Erase Complete
DQ
Erase Suspend read on
non Erase Suspend block
1 Reserved
0 Reserved
Note: Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
11/34
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