PDF M965G0115MP0 Data sheet ( Hoja de datos )

Número de pieza	M965G0115MP0
Descripción	1M X 64 Sgram Sodimm Based on 1M X 32 / 2K Refresh
Fabricantes	Samsung Semiconductor
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No Preview Available ! SGRAM MODULE M965G0115MP(Q)0 / M966G0115MP(Q)0 M965G0115MP(Q)0 / M966G0115MP(Q)0 SGRAM SODIMM 1Mx64 SGRAM SODIMM based on 1Mx32, 2K Refresh, 3.3V Synchronous Graphic RAMs GENERAL DESCRIPTION The Samsung M965(6)G0115MP(Q)0 is a 1M bit x 64 Syn- chronous Graphic RAM high density memory module. The Samsung M965(6)G0115MP(Q)0 consists of two CMOS 1M x 32 bit Synchronous Graphic RAMs in 100pin QFP packages www.DataSheemt4oUu.ncotemd on a 144pin glass-epoxy substrate. Five 0.1uF decoupling capacitors are mounted on the printed circuit board for each Synchronous GRAM. The M965(6)G0115MP(Q)0 is a Small Outline Dual In-line Memory Module and is intended for mounting into 144-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable laten- cies and burst lengths allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. FEATURE • Performance range Part NO. Max. Freq. (tCC) M965(6)G0115MP(Q)0-C50 200MHz (5ns) @CL=3 M965(6)G0115MP(Q)0-C60 166MHz (6ns) @CL=3 M965(6)G0115MP(Q)0-C70 143MHz (7ns) @CL=3 M965(6)G0115MP(Q)0-C80 125MHz (8ns) @CL=3 * M965(6)G0115MP0 : based on PQFP Component M965(6)G0115MQ0 : based on TQFP Component • Burst Mode Operation • BLOCK-WRITE and Write-per-bit capability • Independent byte operation via DQM0 ~ 7 • Auto & Self Refresh Capability (2048 cycles / 32ms) • LVTTL compatible inputs and outputs • Single 3.3V±0.3V power supply • MRS cycle with address key programs. CAS Latency (2, 3) Burst Length (1, 2, 4, 8 & Full page) Data Scramble (Sequential & Interleave) • Optional Serial PD with EEPROM (M966G0115M) • Resistor Strapping Options for speed and CAS Latency • PCB : Height(1000mil), single sided components PIN CONFIGURATIONS (Front Side / Back Side) PIN NAMES Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 VSS 2 VSS 3 DQ63 4 DQ62 Voltage Key 95 DQ31 96 DQ30 97 DQ29 98 DQ28 5 DQ61 6 DQ60 51 RSVD 52 RSVD 99 DQ27 100 DQ26 7 DQ59 8 DQ58 53 RSVD 54 RSVD 101 DQ25 102 DQ24 9 DQ57 10 DQ56 55 VSS 56 VSS 103 VSS 104 VSS 11 VDD 12 VDD 57 DSF 58 RFU 105 DQ23 106 DQ22 13 DQ55 14 DQ54 59 RFU 60 RFU 107 DQ21 108 DQ20 15 DQ53 16 DQ52 61 RFU 62 *SBA 109 DQ19 110 DQ18 17 DQ51 18 DQ50 63 VDD 64 VDD 111 DQ17 112 DQ16 19 DQ49 20 DQ48 65 CS1 66 CS0 113 VDD 114 VDD 21 VSS 22 VSS 67 RAS 68 CAS 115 DQM3 116 DQM2 23 DQM7 24 DQM6 69 WE 70 CKE 117 DQM1 118 DQM0 25 DQM5 26 DQM4 71 VSS 72 VSS 119 VSS 120 VSS 27 VDD 28 VDD 73 CLK1 74 CLK0 121 DQ15 122 DQ14 29 DQ47 30 DQ46 75 VDD 76 VDD 123 DQ13 124 DQ12 31 DQ45 32 DQ44 77 RSVD 78 RSVD 125 DQ11 126 DQ10 33 DQ43 34 DQ42 79 A10 80 A9 127 DQ9 128 DQ8 35 DQ41 36 DQ40 129 VDD 130 VDD 37 VSS 38 VSS 81 BA 82 A8/AP 131 DQ7 132 DQ6 39 DQ39 40 DQ38 83 A7 84 A6 133 DQ5 134 DQ4 41 DQ37 42 DQ36 85 VSS 86 VSS 135 DQ3 136 DQ2 43 DQ35 44 DQ34 87 A5 88 A4 137 DQ1 138 DQ0 45 DQ33 46 DQ32 89 A3 90 A2 139 VSS 140 VSS 47 VDD 48 VDD 91 A1 92 A0 141 SDA 142 SCL 49 RSVD 50 RSVD 93 VDD 94 VDD 143 VDD 144 VDD Pin Name Function A0 ~ A10 Address Input(multiplexed) BA Bank Select Address DQ0 ~ 63 Data Input / Output CLK0, CLK1 Clock Input CKE Clock Enable Input CS0, CS1 Chip Select Input RAS Row Address Strobe CAS Column Address Strobe WE Write Enable DSF Define Special Function DQM0 ~ 7 DQM VDD Power Supply (3.3V) VSS Ground SDA Serial Address Data I/O SBA EEPROM Device Address SCL Serial Clock RSVD Reserved RFU Reserved for future use NC No Connection These pins are not used in this module. ** These pins should be NC in the system which does not support SPD. SAMSUNG ELECTRONICS CO. Ltd. reserves the right to change products and specifications without notice. 1 page SGRAM MODULE M965G0115MP(Q)0 / M966G0115MP(Q)0 DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C, VIH(min)/VIL(max)=2.0V/0.8V) Parameter Operating Current (One Bank Active) Symbol Test Condition ICC1 Burst Length =1 tRC ≥ tRC(min), tCC ≥ tCC(min), Io = 0 mA CAS Latency Speed -50 -60 -70 Unit Note -80 3 400 360 320 300 mA 2 2 - - - 300 Precharge Standby Current in ICC2P www.DataSheetp4oUw.ceorm-down mode ICC2PS Precharge Standby Current in non power-down mode ICC2N ICC2NS CKE ≤ VIL(max), tCC = 15ns CKE & CLK ≤ VIL(max), tCC = ∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns Input signals are changed one time during 30ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 4 mA 4 60 mA 30 Active Standby Current in power-down mode Active Standby Current in non power-down mode (One Bank Active) ICC3P ICC3PS ICC3N ICC3NS CKE ≤ VIL(max), tCC = 15ns CKE & ≤ VIL(max), tCC = ∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns Input signals are changed one time during 30ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 6 mA 6 100 mA 60 Operating Current (Burst Mode) Refresh Current Self Refresh Current Operating Current (One Bank Block Write) ICC4 Io = 0 mA, Page Burst All bank Activated, tCCD = tCCD(min) ICC5 ICC6 ICC7 tRC ≥ tRC(min) CKE ≤ 0.2V tCC ≥ tCC(min), Io=0mA, tBWC(min) 3 580 520 460 400 mA 2 2 - - - 320 3 400 360 320 300 mA 3 2 - - - 300 4 mA 460 400 340 300 mA Note : 1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL. 2. Measured with outputs open. Address are changed only one time during tcc(min). 3. Refresh period is 32ms. Address are changed only one time during tcc(min). 5 Page SGRAM MODULE M965G0115MP(Q)0 / M966G0115MP(Q)0 BURST SEQUENCE (BURST LENGTH = 4) Initial address A1 A0 Sequential Interleave 0001230123 0112301032 1023012301 1130123210 www.DataSheet4U.com BURST SEQUENCE (BURST LENGTH = 8) Initial address A2 A1 A0 Sequential Interleave 0000123456701234567 0011234567010325476 0102345670123016745 0113456701232107654 1004567012345670123 1015670123454761032 1106701234567452301 1117012345676543210 PIXEL to DQ MAPPING(at BLOCK WRITE) Column address A2 A1 A0 000 001 010 011 100 101 110 111 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte I/O63 - I/O56 I/O55 - I/O48 I/O47 - I/O40 I/O39 - I/O32 I/O31 - I/O24 I/O23 - I/O16 DQ56 DQ48 DQ40 DQ32 DQ24 DQ16 DQ57 DQ49 DQ41 DQ33 DQ25 DQ17 DQ58 DQ50 DQ42 DQ34 DQ26 DQ18 DQ59 DQ51 DQ43 DQ35 DQ27 DQ19 DQ60 DQ52 DQ44 DQ36 DQ28 DQ20 DQ61 DQ53 DQ45 DQ37 DQ29 DQ21 DQ62 DQ54 DQ46 DQ38 DQ30 DQ22 DQ63 DQ55 DQ47 DQ39 DQ31 DQ23 1 Byte I/O15 - I/O8 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 0 Byte I/O7 - I/O0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 11 Page

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