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PDF XC3SD1800A Data sheet ( Hoja de datos )

Número de pieza XC3SD1800A
Descripción (XC3SD1800A / XC3SD3400A) Spatran-3A DSP FPGA Family
Fabricantes Xilinx 
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0
R Spartan-3A DSP FPGA Family:
Data Sheet
DS610 July 16, 2007
00
Product Specification
Module 1:
Introduction and Ordering Information
DS610-1 (v2.0) July 16, 2007
• Introduction
• Features
• Architectural Overview
• Configuration Overview
• General I/O Capabilities
www.DataSheeSt4uUp.pcoomrted Packages and Package Marking
• Ordering Information
Module 2:
Functional Description
DS610-2 (v2.0) July 16, 2007
The functionality of the Spartan™-3A DSP FPGA family is
described in the following documents.
UG331: Spartan-3 Generation FPGA User Guide
- Clocking Resources
- Digital Clock Managers (DCMs)
- Block RAM
- Configurable Logic Blocks (CLBs)
· Distributed RAM
· SRL16 Shift Registers
· Carry and Arithmetic Logic
- I/O Resources
- Programmable Interconnect
- ISETM Software Design Tools and IP Cores
- Embedded Processing and Control Solutions
- Pin Types and Package Overview
- Package Drawings
- Powering FPGAs
- Power Management
UG431: XtremeDSP™ DSP48A for Spartan-3A DSP FPGAs
User Guide
- DSP48A Slice Design Considerations
- DSP48A Architecture Highlights
· 18 x 18-Bit Multipliers
· 48-Bit Accumulator
· 18-bit Pre-Adder
- DSP48A Application Examples
UG332: Spartan-3 Generation Configuration User Guide
- Configuration Overview
- Configuration Pins and Behavior
- Bitstream Sizes
- Detailed Descriptions by Mode
· Master Serial Mode using Platform Flash PROM
· Master SPI Mode using Commodity Serial Flash
· Master BPI Mode using Commodity Parallel Flash
· Slave Parallel (SelectMAP) using a Processor
· Slave Serial using a Processor
· JTAG Mode
- ISE iMPACT Programming Examples
- MultiBoot Reconfiguration
- Design Authentication using Device DNA
Module 3:
DC and Switching Characteristics
DS610-3 (v2.0) July 16, 2007
• DC Electrical Characteristics
- Absolute Maximum Ratings
- Supply Voltage Specifications
- Recommended Operating Conditions
• Switching Characteristics
- I/O Timing
- Configurable Logic Block (CLB) Timing
- Digital Clock Manager (DCM) Timing
- Block RAM Timing
- XtremeDSP Slice Timing
- Configuration and JTAG Timing
Module 4:
Pinout Descriptions
DS610-4 (v2.0) July 16, 2007
• Pin Descriptions
• Package Overview
• Pinout Tables
• Footprint Diagrams
SPARTAN-3A DSP
www.xilinx.com/spartan3adsp
© 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS610 July 16, 2007
Product Specification
www.xilinx.com
1

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XC3SD1800A pdf
R Introduction and Ordering Information
IOBs
DCM
CLB
www.DataSheet4U.com
IOBs
DCM
CLBs
DCM
IOBs
DS610-1_01_031207
Notes:
1. The XC3SD1800A and XC3SD3400A have two DCMs on both the left and right sides, as well as the two DCMs at the top and
bottom of the devices. The two DCMs on the left and right of the chips are in the middle of the outer Block RAM/DSP48A
columns of the 4 or 5 columns in the selected device, as shown in the diagram above.
2. A detailed diagram of the DSP48A can be found in UG431: XtremeDSP DSP48A for Spartan-3A DSP FPGAs User Guide.
Figure 1: Spartan-3A DSP Family Architecture
Table 2: Available User I/Os and Differential (Diff) I/O Pairs
Device
User
CS484
CSG484
XC3SD1800A
309
(60)
XC3SD3400A
309
(60)
Diff
140
(78)
140
(78)
User
519
(110)
469
(60)
FG676
FGG676
Diff
227
(131)
213
(117)
Notes:
1. The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number of
input-only pins. The differential (Diff) input-only pin count includes both differential pairs on input-only pins and differential pairs on I/O pins within I/O
banks that are restricted to differential inputs.
DS610-1 (v2.0) July 16, 2007
Product Specification
www.xilinx.com
5

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XC3SD1800A arduino
R
DS610-3 (v2.0) July 16, 2007
<BL
Blue
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Spartan-3A DSP FPGA Family:
DC and Switching Characteristics
0 Product Specification
DC Electrical Characteristics
In this section, specifications may be designated as
Advance, Preliminary, or Production. These terms are
defined as follows:
Advance: Initial estimates are based on simulation, early
characterization, and/or extrapolation from the
characteristics of other families. Values are subject to
www.DatacShhaeentg4Ue.cUomse as estimates, not for production.
Preliminary: Based on characterization. Further changes
are not expected.
Production: These specifications are approved once the
silicon has been characterized over numerous production
lots. Parameter values are considered stable with no future
changes expected.
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. Unless
otherwise noted, the published parameter values apply
to all Spartan™-3A DSP devices. AC and DC
characteristics are specified using the same numbers
for both commercial and industrial grades.
Absolute Maximum Ratings
Stresses beyond those listed under Table 3: Absolute
Maximum Ratings may cause permanent damage to the
device. These are stress ratings only; functional operation
of the device at these or any other conditions beyond those
listed under the Recommended Operating Conditions is not
implied. Exposure to absolute maximum conditions for
extended periods of time adversely affects device reliability.
Table 3: Absolute Maximum Ratings
Symbol
Description
Conditions
Min Max Units
VCCINT
VCCAUX
VCCO
VREF
VIN
Internal supply voltage
Auxiliary supply voltage
Output driver supply voltage
Input reference voltage
Voltage applied to all User I/O pins and
Dual-Purpose pins
Driver in a high-impedance state
–0.5
–0.5
–0.5
–0.5
–0.95
1.32
3.75
3.75
VCCO + 0.5
4.6
V
V
V
V
V
VESD
Voltage applied to all Dedicated pins
Electrostatic Discharge Voltage
Human body model
Charged device model
Machine model
–0.5 4.6
±2000
±500
±200
V
V
V
V
TJ
TSTG
Junction temperature
Storage temperature
– 125 °C
–65 150 °C
Notes:
1. For soldering guidelines, see UG112: Device Packaging and Thermal Characteristics and XAPP427: Implementation and Solder Reflow
Guidelines for Pb-Free Packages.
© 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS610-3 (v2.0) July 16, 2007
Product Specification
www.xilinx.com
11

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