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PDF W65C02S Data sheet ( Hoja de datos )
| Número de pieza | W65C02S | |
| Descripción | Microprocessor | |
| Fabricantes | WDC | |
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The Western Design Center, Inc.
February 2004
W65C02S Data Sheet
www.DataSheet4U.com
W65C02S
Microprocessor
DATA SHEET
© The Western Design Center, Inc., 2003. All rights reserved
WDC
1 page  
The Western Design Center, Inc.
1 INTRODUCTION
W65C02S Data Sheet
The W65C02S is a low power cost sensitive 8-bit microprocessor. The W65C02S is a fully static core and the PHI2 clock
can be stopped when it is in the high (logic 1) or low (logic 0) state. The variable length instruction set and manually
optimized core size makes the W65C02S an excellent choice for low power System-on-Chip (SoC) designs. The Verilog
RTL model is available for ASIC design flows. WDC, a Fabless Semiconductor Company, provides packaged chips for
evaluation or volume production. To aid in system development, WDC provides a Development System that includes a
www.DataSWhe6e5t4CU0.c2oDmB Developer Board, an In-Circuit Emulator (ICE) and the W65cSDS Software Development System, see
www.westerndesigncenter.com for more information.
1.1 Features of the W65C02S
• 8-bit data bus
• 16-bit address bus provides access to 65,536 bytes of memory space
• 8-bit ALU, Accumulator, Stack Pointer, Index Registers, Processor Status Register
• 16-bit Program Counter
• 69 instructions
• 16 addressing modes
• 212 Operation Codes (OpCodes)
• Vector Pull (VPB) output indicates when interrupt vectors are being addressed
• WAit-for-Interrupt (WAI) and SToP (STP) instructions reduce power consumption, decrease interrupt latency and
provide synchronization with external events
• Variable length instruction set provides for lower power and smaller code optimization over fixed length instruction
set processors
• Fully static circuitry
• Wide operating voltage range, 1.8+/- 5%, 2.5+/- 5%, 3.0+/- 5%, 3.3+/ - 10%, 5.0+/- 5% specified
• Low Power consumption, 150uA@1MHz
The Western Design Center, Inc.
W65C02S Data Sheet
5
5 Page 
The Western Design Center, Inc.
W65C02S Data Sheet
3.11 Reset (RESB)
The Reset (RESB) input is used to initialize the microprocessor and start program execution. The RESB signal must
be held low for at least two clock cycles after VDD reaches operating voltage. Ready (RDY) has no effect while
RESB is being held low. All Registers are initialized by software except the Decimal and Interrupt disable mode
select bits of the Processor Status Register (P) are initialized by hardware. When a positive edge is detected, there
will be a reset sequence lasting seven clock cycles. The program counter is loaded with the reset vector from
locations FFFC (low byte) and FFFD (high byte). This is the start location for program control. RESB should be
www.DataShheeledt4hUi.gcohmafter reset for normal operation.
Processor Status Register (P)
*=software initialized
76
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3.12 Set Overflow (SOB)
A negative transition on the Set Overflow (SOB) pin sets the overflow bit (V) in the status code register. The signal is
sampled on the rising edge of PHI2. SOB was originally intended for fast input recognition because it can be tested
with a branch instruction; however, it is not recommended in new system design and was seldom used in the past.
3.13 SYNChronize with OpCode fetch (SYNC)
The OpCode fetch cycle of the microprocessor instruction is indicated with SYNC high. The SYNC output is
provided to identify those cycles during which the microprocessor is fetching an OpCode. The SYNC line goes high
during the clock cycle of an OpCode fetch and stays high for the entire cycle. If the RDY line is pulled low during
the clock cycle in which SYNC went high, the processor will stop in its current state and will remain in the state
until the RDY line goes high. In this manner, the SYNC signal can be used to control RDY to cause single
instruction execution.
3.14 Power (VDD) and Ground (VSS)
VDD is the positive power supply voltage and VSS is system logic ground.
3.15 Vector Pull (VPB)
The Vector Pull (VPB) output indicates that a vector location is being addressed during an interrupt sequence. VPB
is low during the last interrupt sequence cycles, during which time the processor reads the interrupt vector. The
VPB signal may be used to select and prioritize interrupts from several sources by modifying the vector addresses.
The Western Design Center, Inc.
W65C02S Data Sheet
11
11 Page | ||
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