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PDF SC473 Data sheet ( Hoja de datos )
| Número de pieza | SC473 | |
| Descripción | Single-Phase Single Chip Graphics Core Power Supply | |
| Fabricantes | Semtech | |
| Logotipo |  |
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POWER MANAGEMENT
Description
SC473
Single-Phase Single Chip
Graphics Core Power Supply
Features
The SC473 is a single-phase chip, high-performance PWM
controller designed to power advanced graphic cores. On-
chip support is provided that includes slew-rate controlled
VID transitions.
The SC473 implements hysteretic control technology which
provides the fastest possible transient response while
avoiding the stability issues inherent to classical PWM
www.DatacSohneettr4oUll.ecorms. Eliminating the sense resistors reduces costs
and PCB area, plus increases system efficiency. Integrated
SmartDriver™ technology initially turns on the high-side
driver with ‘soft’ drive to reduce ringing, EMI, and capaci-
tive turn-on of the low side MOSFET, while also increasing
overall efficiency.
Single-Phase Solution with Integrated Drivers
Hysteretic Control for Fast Transient Response
SmartDriver™ for reduced EMI
True Differential Remote (die) Sensing
VID Programmed Voltage
Delayed Power Good Signal with Blanking
Programmable Soft-Start and DAC Slew Control
Programmable OCP Threshold
Supports all Ceramic Decoupling Solutions
24-Pin MLP (4x4)
Lead-Free Package
RoHS and WEEE compliant
Hysteretic operation adaptively reduces the SC473 switch-
ing frequency at light loads. Combined with an automatic
“powersave” mode which prevents negative current flow in
the low-side FET, system efficiency is significantly enhanced
during light loading conditions.
Applications
High Performance Graphics
Embedded Applications
A 5-bit DAC, accurate to 0.85%, sets the output voltage
reference, and implements the voltage range required by
the processor. The DAC slew rate is externally programmed
to minimize transient currents and audible noise. True
differential remote sensing provides accurate point-of-load
regulation at the processor die. Other features include
programmable soft-start, an open-drain PWRGD output,
dual-level over-voltage and programmable over-current pro-
tection. The SC473 is available in a space-saving 4x4mm,
24-pin MLP package.
Updated - Aug 17, 2006
1
www.semtech.com
1 page  
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Parameter
Condition
Current Sensing (CS+, CS-) (Cont.)
Low-Pass Filter
Corner Frequency(1)
Current Limit Combined System (CLSET)
www.DataSCheLetS4Uys.ctoemm Accuracy
CLSET = 1.2V, TG Low
CLSET = 1.2V, TG High
CLSET Input Bias Current
Hysteresis Setting (HYS)
HYS Input Bias Current
HYS Gain (internal hysteresis
setting relative to voltage
applied at HYS pin)
HYS = 1V
OVP and Internal Powergood
Fixed Over-Voltage
Protection Threshold
Power Good Window
Upper Threshold
Power Good Window
Lower Threshold
Power Good Window
Lower Hysteresis
FB Rising Relative DAC
FB Falling Relative DAC
FB Rising Relative DAC
Powergood (PWRGD)
Leakage
On-Resistance
PWRGD
High Impedance VPG = 5V
PWRGD = 0.1V
Power Monitor
PMON Output Voltage
VOUT = 1.2875
TJ = 25 oC
CS+, CS- = 4mV
CS+, CS- = 16mV
Min
50
28
16
4
1.65
+160
-360
30
74
530
Typ
80
7
1.7
+200
-300
50
20
148
590
SC473
Max Units
125 kHz
52
mV
32
|1| μA
|1| μA
10 %
1.75
+240
-240
70
V
mV
mV
mV
1 μA
100 Ω
222
mV
650
© 2006 Semtech Corp.
5
www.semtech.com
5 Page 
SC473
POWER MANAGEMENT
Applications Information (Cont.)
Start-Up and Soft-Off Sequences:
For the SC473 cold start-up, V5 must rise above its under-
voltage lockout (UVLO) threshold (4.4V typ.) The EN signal
may go high either before UVLO or after (preferred). The
DAC drives 120μA (typical) into the soft-start capacitor on
the SS pin. The SS pin and DAC rise slowly until the VID(4:0)
When the voltage hits the lower PWRGD threshold, PWRGD
goes high, and start-up is complete.
www.DataSheet4U.com
In a normal shutdown, the EN signal is driven low, the TG
and BG signals are driven low, tri-stating the power chains.
An approximately 10Ω FET on the FB+ signal discharges
Vcore slowly and prevents normal amounts of leakage from
pulling Vcore high. The DAC is discharged to zero, but the
power regulation circuitry is inactive, and PWRGD is low.
DAC Description:
A +/-0.85% 5-bit digital-to-analog converter (DAC) serves as
the programmable reference source of the Core Compara-
tor. Programming is accomplished by logic voltage levels
applied to the DAC inputs. The VID code vs. the DAC output
is shown in Table 1. The five voltage identification pins are
used to support automatic selection of VOUT voltages.
DAC Slew Rate Control:
The DAC also has integrated slew-rate control with to
charge and discharge the soft-start capacitor. All operat-
ing voltage transitions including soft-start use the 120μA
source to charge the soft-start capacitor.
Power Supply Protection:
during soft-start and VID/DeeperSleep transitions. For
safety, the latch is enabled if the FB voltage exceeds 1.7V
even during VID transitions.
The device will be disabled and latched off when the
internal junction temperature reaches approximately
160°C. Either the power or EN must be recycled to clear
the latch.
Power Monitor:
The SC473 adds a power monitor feature to accurately
predict the graphics CPU power consumption. The power
monitor output depends on the current sensing methodol-
ogy used. The following diagram and equation predict the
ideal PMON output.
DC Voltage Between Two Terminals is:
VDCR = I LOAD x RDCR
L1
RDCR
I LOAD
DRN
Voltage
Between these
two terminals is
Veq
+Vcc_core
Req = Parallel
Combination of Resistors
shown in the box
R28
TH2
33k
R24
18.2k
C54
CS-
IR33 R33
5k
VR33
CS+
R27
16.2k
R30
Power Monitor Implementation for SC473 (DCR Sense)
The UVLO circuit consists of a comparator that monitors
the input supply voltage level, V5. The SC473 is in UVLO
mode when its supply voltage has not ramped above the
upper threshold or dropped below the lower threshold. The
output of the UVLO comparator turns on or off the internal
bias, enables or disables the SC473 output, and initiates
or resets the soft-start timer.
Req = (TH2 + R24)(R28 + R30 + R33) (TH2 + R24 + R28 + R30 + R33)
Veq (VDCR x Req) (Req R27)
IR33 Veq (R28 R30 R33)
VR33 IR33 R33
The OVP circuit of SC473 monitors the processor core VOUT
voltage for an over-voltage condition. If the FB voltage is
200mV greater than the DAC voltage (i.e., out of the pow-
ergood window), the SC473 will latch off and hold the low-
side driver on permanently. Either the power or EN must
be recycled to clear the latch. The latch is disabled
PMON_Ideal V R33 Vcc_core 28.5
Similar exercise can be done for R-SENSE configuration
as shown below:
© 2006 Semtech Corp.
11
www.semtech.com
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet SC473.PDF ] | |
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