DataSheet.es    


PDF GS8322Z36 Data sheet ( Hoja de datos )

Número de pieza GS8322Z36
Descripción (GS8322Z18 - GS8322Z72) 36Mb Pipelined and Flow Through Synchronous NBT SRAM
Fabricantes GSI Technology 
Logotipo GSI Technology Logotipo



Hay una vista previa y un enlace de descarga de GS8322Z36 (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! GS8322Z36 Hoja de datos, Descripción, Manual

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)
119, 165 & 209 BGA
Commercial Temp
Industrial Temp
36Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz133 MHz 2.5
V or 3.3 V VDD
2.5 V or 3.3 V I/O
Features
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/–10% core power supply
www.DataSheet42U.5.coVmor 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119-, 165- or 209-Bump BGA package
Functional Description
The GS8322Z18/36/72 is a 36Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8322Z18/36/72 may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8322Z18/36/72 is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 119-bump, 165-bump or 209-bump BGA package.
Parameter Synopsis
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
tKQ(x18/x36)
tKQ(x72)
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
tKQ
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
-250 -225 -200 -166 -150 -133 Unit
2.5 2.7 3.0 3.5 3.8 4.0 ns
3.0 3.0 3.0 3.5 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.7 7.5 ns
285 265 245 220 210 185 mA
350 320 295 260 240 215 mA
440 410 370 320 300 265 mA
6.5 7.0 7.5 8.0 8.5 8.5 ns
6.5 7.0 7.5 8.0 8.5 8.5 ns
205 195 185 175 165 155 mA
235 225 210 200 190 175 mA
315 295 265 255 240 230 mA
Rev: 11/1/04
1/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology

1 page




GS8322Z36 pdf
www.DataSheet4U.com
GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)
GS8322Z36B Pad Out—119-Bump BGA—Top View (Package B)
1234567
A VDDQ A A A A A VDDQ A
B NC E2 A ADV A E3 NC B
C NC A
A VDD A
A NC C
D
DQC DQPC
VSS
ZQ
VSS DQPB DQB
D
E
DQC DQC
VSS
E1
VSS DQB DQB
E
F
VDDQ
DQC
VSS
G
VSS
DQB
VDDQ
F
G
DQC DQC
BC
A
BB DQB DQB
G
H
DQC DQC
VSS
W
VSS DQB DQB
H
J
VDDQ
VDD
NC
VDD
NC
VDD VDDQ
J
K
DQD DQD
VSS
CK
VSS DQA DQA
K
L
DQD DQD
BD
NC
BA DQA DQA
L
M
VDDQ
DQD
VSS
CKE
VSS
DQA
VDDQ
M
N
DQD DQD
VSS
A1
VSS DQA DQA
N
P
DQD DQPD
VSS
A0
VSS DQPA DQA
P
R NC A LBO VDD FT A NC R
T NC NC A A A A ZZ T
U
VDDQ
TMS
TDI
TCK
TDO
NC VDDQ
U
7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch
Rev: 1.04 11/2004
5/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology

5 Page





GS8322Z36 arduino
GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable
inputs will deactivate the device.
www.DataSheet4U.com
Function
W BA BB BC BD
Read H X X X X
Write Byte “a”
LL HH H
Write Byte “b”
LH L H H
Write Byte “c”
LH H L H
Write Byte “d”
LH H H L
Write all Bytes
LL L L L
Write Abort/NOP
LH H H H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.
The Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write
cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Rev: 1.04 11/2004
11/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet GS8322Z36.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
GS8322Z36(GS8322Z18 - GS8322Z72) 36Mb Pipelined and Flow Through Synchronous NBT SRAMGSI Technology
GSI Technology
GS8322Z36B36Mb Pipelined and Flow Through Synchronous NBT SRAMGSI Technology
GSI Technology
GS8322Z36E36Mb Pipelined and Flow Through Synchronous NBT SRAMGSI Technology
GSI Technology

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar