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PDF LM2524 Data sheet ( Hoja de datos )

Número de pieza LM2524
Descripción Regulating Pulse Width Modulator
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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No Preview Available ! LM2524 Hoja de datos, Descripción, Manual

June 1999
LM2524D/LM3524D
Regulating Pulse Width Modulator
General Description
The LM3524D family is an improved version of the industry
standard LM3524. It has improved specifications and addi-
tional features yet is pin for pin compatible with existing 3524
families. New features reduce the need for additional exter-
nal circuitry often required in the original version.
The LM3524D has a ±1% precision 5V reference. The cur-
rent carrying capability of the output drive transistors has
been raised to 200 mA while reducing VCEsat and increasing
VCE breakdown to 60V. The common mode voltage range of
the error-amp has been raised to 5.5V to eliminate the need
for a resistive divider from the 5V reference.
In the LM3524D the circuit bias line has been isolated from
the shut-down pin. This prevents the oscillator pulse ampli-
tude and frequency from being disturbed by shut-down. Also
at high frequencies (300 kHz) the max. duty cycle per out-
put has been improved to 44% compared to 35% max. duty
cycle in other 3524s.
In addition, the LM3524D can now be synchronized exter-
nally, through pin 3. Also a latch has been added to insure
one pulse per period even in noisy environments. The
LM3524D includes double pulse suppression logic that in-
sures when a shut-down condition is removed the state of
the T-flip-flop will change only after the first clock pulse has
arrived. This feature prevents the same output from being
pulsed twice in a row, thus reducing the possibility of core
saturation in push-pull designs.
Features
n Fully interchangeable with standard LM3524 family
n ±1% precision 5V reference with thermal shut-down
n Output current to 200 mA DC
n 60V output capability
n Wide common mode input range for error-amp
n One pulse per period (noise suppression)
n Improved max. duty cycle at high frequencies
n Double pulse suppression
n Synchronize through pin 3
Block Diagram
© 1999 National Semiconductor Corporation DS008650
DS008650-1
www.national.com

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LM2524 pdf
Typical Performance Characteristics (Continued)
Output Transistor
Saturation Voltage
Output Transistor Emitter
Voltage
Reference Transistor
Peak Output Current
Standby Current
vs Voltage
DS008650-31
Standby Current
vs Temperature
DS008650-32
DS008650-33
Current Limit Sense Voltage
Test Circuit
DS008650-34
DS008650-35
DS008650-36
DS008650-4
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LM2524 arduino
Typical Applications (Continued)
DS008650-17
FIGURE 13. Relation of Switch Timing to Inductor Current in Step-Down Regulator
Neglecting VSAT, VD, and settling IL+ = IL−;
where T = Total Period
The above shows the relation between VIN, Vo and duty
cycle.
as Q1 only conducts during tON.
where: L1 is in Henrys
f is switching frequency in Hz
Also, see LM1578 data sheet for graphical methods of induc-
tor selection.
CALCULATING OUTPUT FILTER CAPACITOR Co:
Figure 13 shows L1’s current with respect to Q1’s tON and
tOFF times (VA is at the collector of Q1). This curent must
flow to the load and Co. Co’s current will then be the differ-
ence between IL, and Io.
Ico = IL − Io
From Figure 13 it can be seen that current will be flowing into
Co for the second half of tON through the first half of tOFF, or
a time, tON/2 + tOFF/2. The current flowing for this time is
IL/4. The resulting Vc or Vo is described by:
The efficiency, η, of the circuit is:
ηMAX will be further decreased due to switching losses in
Q1. For this reason Q1 should be selected to have the maxi-
mum possible fT, which implies very fast rise and fall times.
CALCULATING INDUCTOR L1
For best regulation, the inductor’s current cannot be allowed
to fall to zero. Some minimum load current Io, and thus in-
ductor current, is required as shown below:
Since IL+ = IL− = 0.4Io
Solving the above for L1
11
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