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PDF TC94A58FAG Data sheet ( Hoja de datos )
| Número de pieza | TC94A58FAG | |
| Descripción | single-chip CD processor | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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TC94A58FAG
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC94A58FAG
Single-Chip CD Processor with Built-in Controller
The TC94A58FAG is a single-chip CD processor for digital
servo, which incorporates a 4-bit microcontroller.
The controller features an LCD driver, 4-channel 6-bit AD
converter, 1 port 2-channel 2/3-line or UART serial interface
module, a buzzer, 20-bit general-purpose counter function,
interrupt function, and 8-bit timer/counter. The CPU can select
www.DataSheet4U.comone of four operating clocks (16.9344-MHz, 75-kHz or 32.768-kHz
crystal oscillator and external clock input), facilitating interface
with the CD processor.
The CD processor incorporates sync separation protection and
interpolation, EFM demodulator, error correction, digital
Weight: 0.32 g (typ.)
equalizer for servo, and servo controller. The CD processor also
incorporates a 1-bit DA converter. In combination with the TA2157F/FG/FN/FNG digital servo head amplifier, the
TC94A58FAG can very simply configure an adjustment-free CD player.
Thus, the IC is suitable for CD systems for automobiles and radio-cassette players.
Features
• Single-chip CD processor with on-chip CMOS LCD driver and 4-bit microcontroller
• Operating supply voltage:
CD in operation: VDD = 3.0 to 3.6 V (3.3 V typ.)
CD stopped: VDD = 1.8 to 3.6 V (only CPU in operation)
• Supply current:
CD in operation: IDD = 30 mA (typ.)
CD stopped: IDD = 1.5 mA (CD standby mode, with 16.9344-MHz crystal oscillator, CPU in operation)
CD stopped: IDD = 50 µA (CD standby mode, with 75-kHz crystal oscillator, CPU in operation)
• Operating temperature range: Ta = −40 to 85°C
• Package: LQFP (0.5-mm pitch, 1.4 mm thick)
• E2PROM: TC94AE29FAG
1 2005-12-7
1 page  
Block Diagram
TC94A58FAG
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XI
XO
DVDD
RO
DVSS
LO
DVR
CVDD
CVSS
Clock gene.
X’tal
OSC
CD clock
ZDET
PWM
VREF
DA
VREF
VREF
Data
slicer
RFI
SLCO
SERVO
control
VREF
AD
ROM
RAM
Digital equalizer
Automatic adjustment
circuit
CLV
servo
Sub code decoder
PLL
TMAX
TMAX
PDO
Synchronous
guarantee EFM
decode
VCO
VREF
VREF
VCOF
LPFO
LPFN
DACin,BCKin, LRCKin
Audio out
Digital out
CD Reset
16 k SRAM
Correction circuit
P8-0/MXI/SYSCK (BRK1)
P8-1/MXO/DACin (BRK2)
DACin
CR
OSC
X’tal
OSC
Port8
SBSY
INTR
Timer
Interrupt
cont.
Serial
interface
(SIO)
P7-0/SCK2/RX2 (BRK14)
P7-1/SDIO2/TX2 (BRK15)
P7-2/INTR/SI2 (BRK16)
Port7
MPX
CPU clock
Micon interface
Reset
SBSY
BCK, LRCK, AOUT, DOUT
IPF, SBOK, CLCK, DATA, SFSY
Data Reg (16 bit)
Mask ROM
(16 × 16384 Step)
G-Reg.
RAM
(4 × 512 word)
R/W Buf.
ALU
Program
Counter
Stack Reg.
(16Level)
Instruction
Decoder
Reset
F/F
Power on Reset
AD
Bias
BCK, LRCK, AOUT, DOUT, IPF, SBOK,
BCKin, LRCKin
CLCK, DATA, SFSY, SBSY
conv.
20 bit
counter BUZR
LCD Driver/IO Port2, 3, 4, 5, 6
Port1
SIO
RESET
MVDD
MVSS
5 2005-12-7
5 Page 
Pin
No.
Symbol
Pin Name
Function and Operation
TC94A58FAG
Remarks
23 SLCO
DAC output pin for generating data slice level.
RFI
Zin1
AVDD
VREF
24 RFI
RF signal input pin. The value of Zin1 can be
selected using a CD command.
SLCO
DAC
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25
26
27
28
29
30
31
AVDD
VREF
Power supply pin for analog block. Normally,
VDD = 3.0 to 3.6 V. In CD standby mode, turn
this power supply off.
Analog reference voltage pin. Normally, a
voltage of 1/2 AVDD is supplied
(when VDD = 3.3 V, VREF = 1.65 V).
⎯
⎯
RFZI
RFRP
FEI
SBAD
TEI
RFRP zero-cross signal input pin
RFZI
VREF
AVDD
Zin2
1 kΩ typ. 32 kΩ typ.
CD processor control
input/output pin RF ripple signal input pin
Focus error signal input pin
RFRP
FEI
Sunbeam addition signal input pin
SBAD
Tracking error input pin. The pin is read when
tracking servo is turned on.
TEI
AVDD
32 TEZI
Tracking error/zero-cross signal input pin
TEZI
AVDD
Zin2
VREF
1 kΩ typ. 32 kΩ typ.
33 FOO
34 TRO
Focus equalizer output pin
Tracking equalizer output pin
Rout3
AVDD
A VDD
to
AVSS
11 2005-12-7
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| PDF Descargar | [ Datasheet TC94A58FAG.PDF ] | |
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