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PDF VCT3803A Datasheet ( Hoja de datos )

Número de pieza VCT3803A
Descripción Video/Controller/Teletext IC Family
Fabricantes Micronas Semiconductor 
Logotipo Micronas Semiconductor Logotipo
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VCT3803A datasheet

1 Page

VCT3803A pdf
ADVANCE INFORMATION
Contents, continued
Page
Section Title
113
5.13.
Timer T0 and T1
113
5.13.1.
Features
113
5.13.2.
Operation
114
5.13.3.
Timer Registers
115
5.14.
Capture Compare Module (CAPCOM)
115
5.14.1.
Features
116
5.14.2.
Initialization
116
5.14.3.
Operation of CCC
116
5.14.3.1.
Operation of Subunit
117
5.14.4.
Inactivation
118
5.14.5.
CAPCOM Registers
120
5.15.
Pulse Width Modulator
120
5.15.1.
Features
120
5.15.2.
General
120
5.15.3.
Initialization
120
5.15.4.
Operation
120
5.15.5.
PWM Registers
121
5.16.
Tuning Voltage Pulse Width Modulator
121
5.16.1.
Features
121
5.16.2.
General
122
5.16.3.
Initialization
122
5.16.4.
Operation
122
5.16.5.
TVPWM Registers
123
5.17.
A/D Converter (ADC)
123
5.17.1.
Features
123
5.17.2.
Operation
124
5.17.3.
Measurement Errors
124
5.17.4.
Comparator
125
5.17.5.
ADC Registers
126
5.18.
Ports
126
5.18.1.
Port Assignment
127
5.18.2.
Universal Ports P1 to P3
127
5.18.2.1.
Features
128
5.18.2.2.
Universal Port Mode
128
5.18.3.
Universal Port Registers
129
5.18.4.
I2C Ports P40 and P41
129
5.18.4.1.
Features
130
5.18.5.
Audio Ports P42 to P46
130
5.18.5.1.
Features
131
5.18.6.
CLK20 Output Port
131
5.18.6.1.
Features
132
5.19.
I/O Register Cross Reference
VCT 38xxA
Micronas
5

5 Page

VCT3803A arduino
ADVANCE INFORMATION
VCT 38xxA
2. Video Processing
2.1. Introduction
The VCT 38xxA includes complete video, display, and
deflection processing. In the following sections the
video processing part of the VCT 38xxA will be named
VDP for short.
All processing is done digitally, the video front-end and
video back-end are interfacing to the analog world.
Most functions of the VDP can be controlled by soft-
ware via I2C bus slave interface (see Section 2.15. on
page 32).
2.2.2. Clamping
The composite video input signals are AC-coupled to
the IC. The clamping voltage is stored on the coupling
capacitors and is generated by digitally controlled cur-
rent sources. The clamping level is the back porch of
the video signal. S-VHS chrominance is also AC-cou-
pled. The input pin is internally biased to the center of
the ADC input range. The chrominance inputs for
YCrCb need to be AC-coupled by 220 nF clamping
capacitors. It is strongly recommended to use 5-MHz
anti-alias low-pass filters on each input. Each channel
is sampled at 10.125 MHz with a resolution of 8 bit and
a clamping level of 128.
2.2. Video Front-end
This block provides the analog interfaces to all video
inputs and mainly carries out analog-to-digital conver-
sion for the following digital video processing. A block
diagram is given in Fig. 2–1.
Most of the functional blocks in the front-end are digi-
tally controlled (clamping, AGC, and clock-DCO). The
control loops are closed by the Fast Processor (‘FP’)
embedded in the video decoder.
2.2.3. Automatic Gain Control
A digitally working automatic gain control adjusts the
magnitude of the selected baseband by +6/–4.5 dB in
64 logarithmic steps to the optimal range of the ADC.
The gain of the video input stage including the ADC is
213 steps/V with the AGC set to 0 dB. The gain of the
chrominance path in the YCrCb mode is fix and
adapted to a nominal amplitude of 0.7 Vpp. However, if
an overflow of the ADC occurs an extended signal
range from 1 Vpp can be selected.
2.2.1. Input Selector
2.2.4. Analog-to-Digital Converters
Up to seven analog inputs can be connected. Four
inputs are for input of composite video or S-VHS luma
signal. These inputs are clamped to the sync back
porch and are amplified by a variable gain amplifier.
Two chroma inputs can be used for connection of
S-VHS carrier-chrominance signal. These inputs are
internally biased and have a fixed gain amplifier. For
analog YCrCb signals (e.g. from DVD players) one of
the selected luminance inputs is used together with
CBIN and CRIN inputs.
Two ADCs are provided to digitize the input signals.
Each converter runs with 20.25 MHz and has 8 bit res-
olution. An integrated bandgap circuit generates the
required reference voltages for the converters. The two
ADCs are of a 2-stage subranging type.
VOUT
CVBS/Y
CVBS/Y VIN1
CVBS/Y VIN2
CVBS/Y VIN3
CVBS/Y VIN4
Chroma CIN1
Chroma
CIN2
CRIN
Chroma CBIN
Clamp
Bias
Clamp
AGC
+6/–4.5 dB
3
ADC
digital CVBS or Luma
Gain
ADC
digital Chroma
Reference
Generation
DVCO
±150
ppm
System Clocks
Frequency
20.25 MHz
Fig. 2–1: Video front-end
Micronas
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