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PDF EDL5132CBMA Data sheet ( Hoja de datos )
| Número de pieza | EDL5132CBMA | |
| Descripción | 512M bits Mobile RAM MCP 2 pcs of 256Mb components | |
| Fabricantes | Elpida Memory | |
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PRELIMINARY DATA SHEET
512M bits Mobile RAM MCP
2 pcs of 256Mb components
EDL5132CBMA (16M words × 32 bits)
Description
Pin Configurations
The EDL5132CBMA is a 512M bits Mobile RAM MCP
(Multi Chip Package) organized as 4,194,304 words ×
32 bits × 4 banks, 2 pieces of 256M bits Mobile RAM in
one package. It is packaged in 90-ball FBGA.
Features
• Low voltage power supply
www.DataSheeVt4DUD.c:om 1.7V to 1.95V
VDDQ: 1.7V to 1.95V
• Wide temperature range (−25°C to 85°C)
• Programmable Partial Array Self Refresh
• Programmable Driver Strength
• Auto Temperature Compensated Self Refresh by
built-in temperature sensor.
• Deep power down mode
• Fully Synchronous Dynamic RAM, with all signals
referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every
cycle
• Quad internal banks controlled by BA0 and BA1
• Byte control by DQM
• Wrap sequence = Sequential/ Interleave
• /CAS latency (CL) = 2, 3
• Automatic precharge and controlled precharge
• Auto refresh and self refresh
• ×32 organization
• 8,192 refresh cycles/64ms
• Burst termination by Burst stop command and
Precharge command
• FBGA package with lead free solder (Sn-Ag-Cu)
/xxx indicates active low signal.
90-ball FBGA
123456789
A
DQ26 DQ24 VSS
B
DQ28 VDDQ VSSQ
C
VSSQ DQ27 DQ25
D
VSSQ DQ29 DQ30
E
VDDQ DQ31 NC
F
VSS DQM3 A3
G
A4 A5 A6
H
A7 A8 A12
J
CLK CKE A9
K
DQM1 NC NC
L
VDDQ DQ8 VSS
M
VSSQ DQ10 DQ9
N
VSSQ DQ12 DQ14
P
DQ11 VDDQ VSSQ
R
DQ13 DQ15 VSS
(Top view)
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC DQ16 VSSQ
A2 DQM2 VDD
A10 A0 A1
NC BA1 A11
BA0 /CS /RAS
/CAS /WE DQM0
VDD DQ7 VSSQ
DQ6 DQ5 VDDQ
DQ1 DQ3 VDDQ
VDDQ VSSQ DQ4
VDD DQ0 DQ2
A0 to A12
BA0, BA1
DQ0 to DQ31
/CS
/RAS
/CAS
/WE
DQM0 to DQM3
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Address inputs
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
DQ mask enable
Clock enable
Clock input
Power supply
Ground
Power supply for DQ
Ground for DQ
No connection
Document No. E0490E30 (Ver. 3.0)
Date Published September 2004 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004
1 page  
EDL5132CBMA
DC Characteristics 1 (TA = –25 to +85°C, VDD = VDDQ = 1.7V to 1.95V, VSS, VSSQ = 0V)
Parameter
/CAS latency
Operating current
(CL = 2)
(CL = 3)
Standby current in power down
Standby current in power down
(input signal stable)
Symbol
IDD1
IDD1
IDD2P
IDD2PS
Grade
max.
80
80
1.2
1
Standby current in non power down IDD2N
6
Standby current in non power down
(input signal stable)
Active standby current in power down
Active standby current in power down
(input signal stable)
www.DataSheet4U.com
Active standby current in non power
down
IDD2NS
IDD3P
IDD3PS
IDD3N
Active standby current in non power
down (input signal stable)
Burst operating current
(CL = 2)
(CL = 3)
Refresh current
(CL = 2)
(CL = 3)
Standby current in deep power down
mode
IDD3NS
IDD4
IDD4
IDD5
IDD5
IDD7
4
2
1.6
30
10
90
120
110
110
20
Unit Test condition
mA Burst length = 1
tRC ≥ tRC min., IO = 0mA,
mA One bank active
mA CKE ≤ VIL max., tCK = 15ns
mA CKE ≤ VIL max., tCK = ∞
CKE ≥ VIH min., tCK = 15ns,
mA /CS ≥ VIH min.,
Input signals are changed one
time during 30ns.
mA
CKE ≥ VIH min., tCK = ∞,
Input signals are stable.
mA CKE ≤ VIL max., tCK = 15ns
mA CKE ≤ VIL max., tCK = ∞
CKE ≥ VIH min., tCK = 15 ns,
mA /CS ≥ VIH min.,
Input signals are changed one
time during 30ns.
mA
CKE ≥ VIH min., tCK = ∞,
Input signals are stable.
mA
tCK ≥ tCK min.,
IOUT = 0mA, All banks active
mA
mA tRC ≥ tRC min.
mA
µA CKE ≤ 0.2V
Notes
1
2
3
Self refresh current
Symbol Grade typ.
max.
Unit Condition
Notes
PASR="000" (Full)
PASR="001" (2BK)
PASR="010" (1BK)
IDD6
800
µA
TA ≤ 85°C +0°C/−15°C,
CKE ≤ 0.2V
4
600 µA
500 µA
PASR="000" (Full)
IDD6
400
µA TA ≤ 45°C, CKE ≤ 0.2V 4
PASR="001" (2BK)
360
µA
PASR="010" (1BK)
300
µA
Notes: 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open.
In addition to this, IDD1 is measured on condition that addresses are changed only one time during
tCK (min.).
2. IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open.
In addition to this, IDD4 is measured on condition that addresses are changed only one time during
tCK (min.).
3. IDD5 is measured on condition that addresses are changed only one time during tCK (min.).
4. IDD6 is specified when self refresh state is maintained long enough under the specified TA condition, after
a busy sequence of read and write operations.
Preliminary Data Sheet E0490E30 (Ver. 3.0)
5
5 Page 
EDL5132CBMA
Pin Function
CLK (input pin)
CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge.
CKE (input pins)
CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is valid; otherwise it is
invalid. If the CLK rising edge is invalid, the internal clock is not issued and the Mobile RAM suspends operation.
When the Mobile RAM is not in burst mode and CKE is negated, the device enters power down mode. During power
down mode, CKE must remain low.
/CS (input pins)
/CS low starts the command input cycle. When /CS is high, commands are ignored but operations continue.
/RAS, /CAS, and /WE (input pins)
/RAS, /CAS and /WE have the same symbols on conventional DRAM but different functions. For details, refer to the
command table.
www.DataSAh0eetto4UA.c1o2m(input pins)
Row Address is determined by A0 to A12 at the CLK (clock) rising edge in the active command cycle. It does not
depend on the bit organization.
Column Address (See “Address Pins Table”) is determined by A0 to A8 at the CLK rising edge in the read or write
command cycle.
[Address Pins Table]
Address (A0 to A12)
Part Number
Row addresss
Column address
EDL5132CB
AX0 to AX12
AY0 to AY8
A10 defines the precharge mode. When A10 is high in the precharge command cycle, all banks are precharged;
when A10 is low, only the bank selected by BA0 and BA1 is precharged.
When A10 is high in read or write command cycle, the precharge starts automatically after the burst access.
BA0 and BA1 (input pin)
BA0 and BA1 are bank select signal. (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0
Bank A
L
Bank B
H
Bank C
L
Bank D
H
Remark: H: VIH. L: VIL.
BA1
L
L
H
H
Preliminary Data Sheet E0490E30 (Ver. 3.0)
11
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| PDF Descargar | [ Datasheet EDL5132CBMA.PDF ] | |
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