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PDF DS1680 Data sheet ( Hoja de datos )

Número de pieza DS1680
Descripción Portable System Controller
Fabricantes Dallas Semiconductor 
Logotipo Dallas Semiconductor Logotipo



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www.maxim-ic.com
FEATURES
§ Real-time clock (RTC)
Counts seconds, minutes, hours, date,
month, day of the week, and year with
leap-year compensation valid up to 2100
Power control circuitry supports system
power-on from day/time alarm
§ Microprocessor monitor
Halts microprocessor during power- fail
Automatically restarts microprocessor
after power failure
Monitors pushbutton for external
override
Halts and resets an out of control
microprocessor
§ NV RAM control
Automatic battery backup and write
protection to external SRAM
§ 1.25V threshold detector for power- fail
warning
§ 10-bit analog-to-digital converter (ADC)
Monotonic with no missing codes
§ Four-wire analog resistive touch-screen
interface
DS1680
Portable System Controller
with Touch-Screen Control
PIN ASSIGNMENT
VBAT
X1
44
1
X2
AVG
BHE
COEN
OUT_SELECT
CONVERT
PD_RESET
PEN_SELECT
ANSELIN
11
12
34
33
PFI
GND
D7
D6
D5
D4
D3
D2
D1
D0
NEW_DATA
23
22
44-Pin MQFP (10 x 10 x 2mm)
Package dimension information can be found at:
http://www.maxim-ic.com/TechSupport/DallasPackInfo.htm
ORDERING INFORMATION
DS1680FP-3
3.3V Operation
DS1680FP-5
5.0V Operation
DESCRIPTION
The DS1680 incorporates many functions necessary for low-power portable products, providing an RTC,
NV RAM controller, microprocessor monitor, power- fail warning, 10-bit ADC, and a touch-screen
controller in one chip.
The RTC provides seconds, minutes, hours, day, date, month, and year information with leap-year
compensation as well as an alarm interrupt. This interrupt works when the DS1680 is powered by the
system power supply or when in battery-backup operation, so the alarm can be used to wake up a system
that is powered down.
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DS1680
3-WIRE SERIAL INTERFACE
Communication with the RTC and watchdog is accomplished through a simple 3-wire interface
consisting of the chip select (CS), serial clock (SCLK), and input/output (I/O) pins.
All data transfers are initiated by driving the CS input high. The CS input serves two functions. First, CS
turns on the control logic, which allows access to the shift register for the address/command sequence.
Second, the CS signal provides a method of terminating either single byte or multip le byte (burst) data
transfer. A clock cycle is a sequence of a rising edge followed by a falling edge. For data input, data must
be valid during the clock’s rising edge and data bits are output on the clock’s falling edge. If the CS input
goes low, all data transfer terminates and the I/O pin goes to a high- impedance state.
Address and data bytes are always shifted LSB first into the I/O pin. Any transaction requires the
address/command byte to specify a read or write to a specific register followed by one or more bytes of
data. The address byte is always the first byte entered after CS is driven high. The most significant bit
( RD /WR) of this byte determines if a read or write will take place. If this bit is 0, one or more read cycles
will occur. If this bit is 1, one or more write cycles will occur.
Data transfers can occur one byte at a time or in multiple-byte burst mode. After CS is driven high an
address is written to the DS1680. After the address, one or more data bytes can be read or written. For a
single byte transfer one byte is read or written and then CS is driven low. Multiple bytes can be read or
written to the DS1680 after the address has been written. Each read or write cycle causes the register
address to automatically increment. Incrementing continues until the device is disabled. After accessing
register 0Dh, the address wraps to 00h.
Data transfer for single-byte transfer and multiple-byte burst transfer is illustrated in Figures 2 and 3.
SINGLE-BYTE DATA TRANSFER Figure 2
MULTIPLE-BYTE BURST TRANSFER Figure 3
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DS1680
RESISTIVE TOUCH SCREEN (4-WIRE)
Resistive touch screens consist of two resistive plates that are separated by a small gap. Each plate has an
electrode at each end; when the screen is touched the pressure forces the two plates to come in contact at
the exact position of the touch. To get the x-coordinate position, the DS1680 will drive the X-plane
resistive film (via X+ and X-) and sense the voltage picked up by the Y-plane resistive film (via Y+ and
Y-). Next, to get the y-coordinate position, the DS1680 will drive the Y- plane resistive film and sense the
voltage picked up by the X-plane resistive film.
ANALOG-TO-DIGITAL CONVERTER (ADC)
The DS1680 provides a 10-bit ADC. Two multiplexed analog inputs are provided through the AIN0 and
AIN1 pins along with two other inputs on the X- and Y- pins. The ADC is monotonic (no missing codes)
and uses a successive approximation technique to convert the analog signal into a digital code.
An analog-to-digital conversion is the process of assigning a digital code to an analog input voltage. This
code represents the input value as a fraction of the full-scale voltage (FSV) range. The FSV range is then
divided by the ADC into 1024 codes (10 bits), and is bound by an upper limit equal to the reference
voltage and the lower limit, which is ground.
On-chip circuitry detects if the pen is in contact with the digitizer tablet. The pen-detection status is
indicated on pin (PEN_OFF) and can be used by the system for signaling end-of-stroke for handwriting
recognition software purposes. If no pen is detected, PEN_OFF will be pulled to logic 1 and no
coordinate data will be made available. PEN_OFF at logic 0 indicates that a pen is detected on the
digitizer tablet and its coordinate position will be made available on D0–D7. The NEW_DATA pin
pulses low to indicate when a new coordinate data pair is available.
When the AVG pin is set to logic 0, the data at pins D0–D7 will indicate the most recent sample of the
ADC. Setting the AVG pin to logic 1 invokes the data averaging mode. In this mode, the data output on
D0–D7 will indicate the rolling average of the four most recent samples of the ADC.
The DS1680 continuously monitors the CONVERT and ANSELIN signals; on the internal clock’s rising
edge (state cycle), the corresponding AIN0 or AIN1 conversion is requested. The conversion request
must be completed before T0 (Figure 7c) in order for AIN0 and/or AIN1 to be sampled and converted in
the present conversion cycle; otherwise AIN0 and/or AIN1 will be sampled and converted in the next
conversion cycle. The logic level of the ANSELIN input will determine whether a sample is taken from
the AIN0 or AIN1 input. Table 3 lists the specific analog input that is selected by this signal. Figure 8
shows the required timing associated with CONVERT and ANSELIN. If the state of ANSELIN changes
while CONVERT is at logic 1 and you meet the timing requirements of figure 8, both AIN0 and AIN1
conversions are requested. If the ANSELIN does not change states while CONVERT is at
logic 1, only AIN0 or AIN1 conversion is requested. If a pen is detected during a conversion request, then
X and Y will be sampled and converted prior to the AIN0 and/or AIN1 conversion. The AIN0 and AIN1
conversion result is output on the D0–D7 as defined in the Parallel Interface section.
ANALOG INPUT SELECTION Table 3
ANSELIN
ANALOG INPUT
0 AINO
1 AIN1
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