PDF LM2326 Datasheet ( Hoja de datos )

Número de pieza LM2326
Descripción PLLatinum Low Power Frequency Synthesizer for RF Personal Communications
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo

Total 19 Páginas
LM2326 Hoja de datos, Descripción, Manual
April 2000
PLLatinumLow Power Frequency Synthesizer for RF
Personal Communications
LMX2306 550 MHz
LMX2316 1.2 GHz
LMX2326 2.8 GHz
General Description
The LMX2306/16/26 are monolithic, integrated frequency
synthesizers with prescalers that are designed to be used to
generate a very stable low noise signal for controlling the lo-
cal oscillator of an RF transceiver. They are fabricated using
National’s ABiC V silicon BiCMOS 0.5µ process.
The LMX2306 contains a 8/9 dual modulus prescaler while
the LMX2316 and the LMX2326 have a 32/33 dual modulus
prescaler. The LMX2306/16/26 employ a digital phase
locked loop technique. When combined with a high quality
reference oscillator and loop filter, the LMX2306/16/26 pro-
vide the feedback tuning voltage for a voltage controlled os-
cillator to generate a low phase noise local oscillator signal.
Serial data is transferred into the LMX2306/16/26 via a three
wire interface (Data, Enable, Clock). Supply voltage can
range from 2.3V to 5.5V. The LMX2306/16/26 feature ultra
low current consumption; LMX2306 - 1.7 mA at 3V,
LMX2316 - 2.5 mA at 3V, and LMX2326 - 4.0 mA at 3V.
The LMX2306/16/26 synthesizers are available in a 16-pin
TSSOP surface mount plastic package.
n 2.3V to 5.5V operation
n Ultra low current consumption
n 2.5V VCC JEDEC standard compatible
n Programmable or logical power down mode:
— ICC = 1 µA typical at 3V
n Dual modulus prescaler:
— LMX2306
— LMX2316/26
n Selectable charge pump TRI-STATE® mode
n Selectable FastLockmode with timeout counter
n MICROWIREInterface
n Digital Lock Detect
n Portable wireless communications (PCS/PCN, cordless)
n Wireless Local Area Networks (WLANs)
n Cable TV tuners (CATV)
n Pagers
n Other wireless communication systems
Functional Block Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FastLock, PLLatinumand MICROWIREare trademarks of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation DS100127

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LM2326 pdf
Charge Pump Current Specification Definitions
I1 = CP sink current at VCPo = VpV
I2 = CP sink current at VCPo = Vp/2
I3 = CP sink current at VCPo = V
I4 = CP source current at VCPo = VpV
I5 = CP source current at VCPo = Vp/2
I6 = CP source current at VCPo = V
V = Voltage offset from positive and negative rails. Dependent on VCO tuning range relative to VCC and ground. Typical values
are between 0.5V and 1.0V
1. ICPo vs VCPo = Charge Pump Output Current magnitude variation vs Voltage =
[12 * { |I1| − |I3|}]/[12 * {|I1| + |I3|}] * 100% and [12 * {|I4| − |I6|}]/[12 * {|I4| + |I6|}] * 100%
2. ICPo-sink vs ICPo–source = Charge Pump Output Current Sink vs Source Mismatch =
[|I2| − |I5|]/[12 * {|I2| + |I5|}] * 100%
3. ICPo vs T = Charge Pump Output Current magnitude variation vs Temperature =
[|I2 @ temp| − |I2 @ 25˚C|]/|I2 @ 25˚C| * 100% and [|I5 @ temp| − |I5 @ 25˚C|]/|I5 @ 25˚C| * 100%

5 Page

LM2326 arduino
1.0 Functional Description (Continued)
Output provided to indicate when the VCO frequency is in “lock.” When the loop is locked and the open drain lock detect mode
is selected, the pin’s output is HIGH, with narrow pulses LOW. When digital lock detect is selected, the output will be HIGH when
the absolute phase error is < 15 ns for three or five consecutive phase frequency detector reference cycles, depending on the
value of R[19]. Once lock is detected the output stays HIGH unless the absolute phase error exceeds 30 ns for a single reference
cycle. Setting the charge pump to TRI-STATE or power down (bits F2, F18) will reset the digital lock detect to the unlocked state.
The LD precision bit, R[19], will select five consecutive reference cycles, instead of three, for entering the locked state when R[19]
FIGURE 1. Typical Lock Detect Circuit
The component values for the open drain lock detect filter can be determined after assessing the qualifications for an in-lock con-
dition. The in-lock condition can be specified as being a particular number (N) of consecutive reference cycles or duration (D)
wherein the phase detector phase error is some factor less than the reference period. In an example where the phase detector
reference period is 10 kHz, one might select the threshold for in-lock as occurring when 5 consecutive phase comparisons have
elapsed where the phase errors are a 1000 times shorter than the reference period (100 ns). Here, N = 5 and F = 1000.
For the lock detect filter shown in Figure 1, when used in conjunction with a open drain (active sink only) lock detect output, the
resistor value for R2 would be chosen to be a factor of F * R1. Thus, if resistor R1 were pulled low for only 1/1000th of the ref-
erence cycle period, its “effective” resistance would be on par with R2. The two resistors for that duty cycle condition on average
appear to be two 1000x R1 resistors connected across the supply voltage with their common node voltage (Vc) at VCC/2. Phase
errors larger than 1/1000th of the reference cycle period would drag the average voltage of node Vc below VCC/2 indicating an
out-of-lock status. If the time constant of R2 * C1 is now calculated to be N * the reference period (500 µs), then the voltage of
node Vc would fall below VCC/2 only after 5 consecutive phase errors whose average pulse width was greater than 100 ns.
1.3.4 FastLock MODES
FastLock enables the designer to achieve both fast frequency transitions and good phase noise performance by dynamically
changing the PLL loop bandwidth. The FastLock modes allow wide band PLL fast locking with seemless transition to a low phase
noise narrow band PLL. Consistent gain and phase margins are maintained by simultaneously changing charge pump current
magnitude, counter values, and loop filter damping resistor. The four FastLock modes in Table 5 are similar to the technique used
in National Semiconductor’s LMX 233X series Dual Phase Locked Loops and are selected by F9, F10, and N19 when F8 is HIGH.
Modes 1 and 2 change loop bandwidth by a factor of two while modes 3 and 4 change the loop bandwidth by a factor of 4. Modes
1 and 2 increase charge pump magnitude by a factor of 4 and should use R2’=R2 for consistent gain and phase margin. Modes
3 and 4 increase charge pump magnitude and decrease the counter values by a factor of 4. R2’ = 13 R2 should be used for con-
sistent stability margin in modes 3 and 4. When F8 is LOW, the FastLock modes are disabled, F9 controls only the FLo output
level (FLo = F9), and N19 determines the charge pump current magnitude (N19=LOWICPo = 250 µA, N19=HIGHICPo =
1 mA).

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