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PDF CAT93HC46 Data sheet ( Hoja de datos )

Número de pieza CAT93HC46
Descripción 1-kb High Speed Microwire Serial EEPROM
Fabricantes Catalyst Semiconductor 
Logotipo Catalyst Semiconductor Logotipo



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CAT93HC46
1-kb High Speed Microwire Serial EEPROM
FEATURES
s High speed operation: 4 MHz @ 5.0 V
s 1.8 to 5.5 volt operation
s Selectable x8 or x16 word organization
s Sequential Read
s Software write protection
s Power-up inadvertent write protection
ALOGEN FR
LEA D F REETM
s Low power CMOS technology
s 1,000,000 program/erase cycles
s 100 year data retention
s Industrial and extended temperature ranges
s 8-Lead PDIP, SOIC, MSOP and TSSOP
packages
DESCRIPTION
The CAT93HC46 is a 1-kb Serial EEPROM memory
device which is configured as registers of either 16 bits
(ORG pin at VCC) or 8 bits (ORG pin at GND). Each
register can be written (or read) serially by using the DI
(or DO) pin. The CAT93HC46 is manufactured using
Catalyst’s advanced CMOS EEPROM floating gate
technology. The device is designed to endure 1,000,000
program/erase cycles and has a data retention of 100
years. The CAT93HC46 is available in 8-pin DIP, SOIC,
MSOP or TSSOP packages.
PIN CONFIGURATION
DIP Package (P, L) SOIC Package (J, W)
CS 1
SK 2
DI 3
DO 4
8 VCC NC 1
7 NC VCC 2
6 ORG CS 3
5 GND SK 4
8 ORG
7 GND
6 DO
5 DI
SOIC Package (S, V) MSOP Package (R, Z)
CS 1
SK 2
DI 3
DO 4
8 VCC CS 1
7 NC
SK 2
6 ORG DI 3
5 GND DO 4
8 VCC
7 NC
6 ORG
5 GND
TSSOP Package (U, Y)
CS 1
SK 2
DI 3
DO 4
8 VCC
7 NC
6 ORG
5 GND
Note: When the ORG pin is connected to VCC, the X16
organization is selected. When it is connected to ground,
the X8 pin is selected. If the ORG pin is left unconnected,
then an internal pullup device will select the X16
organization.
FUNCTIONAL SYMBOL
VCC
ORG
DI
SK
CS
CAT93HC46
DO
VSS
PIN FUNCTIONS
Pin Name
CS
SK
DI
DO
VCC
GND
ORG
NC
Function
Chip Select
Clock Input
Serial Data Input
Serial Data Output
1.8 to 5.5 V Power Supply
Ground
Memory Organization
No Connection
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1008,Rev. G

1 page




CAT93HC46 pdf
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CAT93HC46
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93HC46
will come out of the high impedance state; after an initial
dummy zero bit, data will be shifted out, MSB first. The
output will toggle on the rising edge of the SK clock and
will be stable after the specified time delay (tPD0 or tPD1)
After the 1st data word has been shifted out and CS
remains asserted with the SK clock continuing to toggle,
the CAT93HC46 will automatically increment to the next
address and shift out the next data word. As long as CS
is continuously asserted and SK continues to toggle, the
device will keep incrementing to the next address
automatically until it reaches the end of the address
space, then loops back to address 0. In the sequential
READ mode, only the initial data word is preceeded by
a dummy zero bit; all subsequent data words will follow
without a dummy zero bit.
Write
After receiving a WRITE command, address and data,
the CS (Chip Select) pin must be deselected for a
minimum of tCSMIN. The falling edge of CS will start the
self-timed clear and data store cycle into the specified
memory location. The clocking of the SK pin is not
necessary after the device has entered the self-timed
mode. (Note 1.) The ready/busy status of the CAT93HC46
can be determined by selecting the device and polling
the DO pin. Since this device features Auto-Clear before
write, it is NOT necessary to erase a memory location
before it is written into.
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a minimum
of tCSMIN. The falling edge of CS will start the self-timed
clear cycle of the selected memory location. The clocking
of the SK pin is not necessary after the device has
entered the self-timed mode. (Note 1.) The ready/busy
status of the CAT93HC46 can be determined by selecting
the device and polling the DO pin. Once cleared, the
content of a cleared location returns to a logical 1state.
Figure 2a. Read Instruction Timing
SK
CS
AN AN1
DI
11
0
A0
HIGH-Z
tPD0
DO 0
DN DN1
tCS MIN
STANDBY
tHZ
D1 D0
HIGH-Z
Figure 2b. Sequential Read Instruction Timing
SK
1 11 1 111 11 1 1 1 1 1 1
CS
AN AN1
DI
11
0
A0
Don't Care
HIGH-Z
DO
Dummy 0
D15 . . . D0
or
D7 . . . D0
Address + 1
D15 . . . D0
or
D7 . . . D0
Address + 2
D15 . . . D0
or
D7 . . . D0
Address + n
D15 . . .
or
D7 . . .
5 Doc. No. 1008, Rev. G

5 Page










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