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PDF V54C365164VD Data sheet ( Hoja de datos )
| Número de pieza | V54C365164VD | |
| Descripción | HIGH PERFORMANCE 225/200/166/143 MHz 3.3 VOLT 4M X 16 SYNCHRONOUS DRAM 4 BANKS X 1Mbit X 16 | |
| Fabricantes | Mosel Vitelic | |
| Logotipo |  |
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MOSEL VITELIC
V54C365164VD(L)
HIGH PERFORMANCE 225/200/166/143 MHz
3.3 VOLT 4M X 16 SYNCHRONOUS DRAM
4 BANKS X 1Mbit X 16
PRELIMINARY
System Frequency (fCK)
Clock Cycle Time (tCK3)
Clock Access Time (tAC3) CAS Latency = 3
Clock Access Time (tAC2) CAS Latency = 2
Clock Access Time (tAC1) CAS Latency = 1
45
225 MHz
4.5 ns
4.5 ns
4.5 ns
12 ns
5
200 MHz
5 ns
5 ns
5 ns
12 ns
6
166 MHz
6 ns
5.4 ns
5.5 ns
12 ns
7
143 MHz
7 ns
5.4 ns
5.5 ns
12 ns
Features
s 4 banks x 1Mbit x 16 organization
s High speed data transfer rates up to 225 MHz
s Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
s Single Pulsed RAS Interface
s Data Mask for byte Control
s Four Banks controlled by BA0 & BA1
s Programmable CAS Latency: 1, 2, 3
s Programmable Wrap Sequence: Sequential or
Interleave
s Programmable Burst Length:
1, 2, 4, 8 and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
s Multiple Burst Read with Single Write Operation
s Automatic and Controlled Precharge Command
s Random Column Address every CLK (1-N Rule)
s Suspend Mode and Power Down Mode
s Auto Refresh and Self Refresh
s Refresh Interval: 4096 cycles/64 ms
s Available in 54 Pin 400 mil TSOP-II
s LVTTL Interface
s Single +3.3 V ±0.3 V Power Supply
Description
The V54C365164VD(L) is a four bank Synchro-
nous DRAM organized as 4 banks x 1Mbit x 16. The
V54C365164VD(L) achieves high speed data trans-
fer rates up to 225 MHz by employing a chip archi-
tecture that prefetches multiple bits and then
synchronizes the output data to a system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
225 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
T
•
Access Time (ns)
45 5
6
7
••• •
Power
Std. L
••
Temperature
Mark
Blank
V54C365164VD(L) Rev. 1.3 September 2001
1
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MOSEL VITELIC
Capacitance*
TA = 0 to 70°C, VCC = 3.3 V ± 0.3 V, f = 1 Mhz
Symbol Parameter
Max. Unit
CI1 Input Capacitance (A0 to A11)
5 pF
CI2 Input Capacitance
5 pF
RAS, CAS, WE, CS, CLK, CKE, DQM
CIO
CCLK
Output Capacitance (I/O)
Input Capacitance (CLK)
6.5 pF
4 pF
*Note:Capacitance is sampled and not 100% tested.
Block Diagram
Column Addresses
A0 - A7, AP, BA0, BA1
Column address
counter
Column address
buffer
Row Addresses
A0 - A11, BA0, BA1
Row address
buffer
V54C365164VD(L)
Refresh Counter
Row decoder
Memory array
Bank 0
4096 x 256
x 16 bit
Row decoder
Memory array
Bank 1
4096 x 256
x 16 bit
Row decoder
Memory array
Bank 2
4096 x 256
x 16 bit
Row decoder
Memory array
Bank 3
4096 x 256
x 16 bit
Input buffer Output buffer
I/O1-I/O16
Control logic & timing generator
V54C365164VD(L) Rev. 1.3 September 2001
5
5 Page 
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MOSEL VITELIC
V54C365164VD(L)
operation. If CA10 is high when a Read Command is
issued, the Read with Auto-Precharge function is
initiated. The SDRAM automatically enters the pre-
charge operation one clock before the last data out
for CAS latencies 2, two clocks for CAS latencies 3
and three clocks for CAS latencies 4. If CAS10 is
high when a Write Command is issued, the Write
with Auto-Precharge function is initiated. The
SDRAM automatically enters the precharge opera-
tion a time delay equal to tWR (Write recovery time)
after the last data in.
Precharge Command
There is also a separate precharge command
available. When RAS and WE are low and CAS is
high at a clock timing, it triggers the precharge oper-
ation. Three address bits, BA0, BA1 and A10 are
used to define banks as shown in the following list.
The precharge command can be imposed one clock
before the last data out for CAS latency = 2, two
clocks before the last data out for CAS latency = 3
and three clocks before the last data out for CAS la-
tency= 4. Writes require a time delay twr from the
last data out to apply the precharge command.
Burst Termination
Once a burst read or write operation has been ini-
tiated, there are several methods in which to termi-
nate the burst operation prematurely. These
methods include using another Read or Write Com-
mand to interrupt an existing burst operation, use a
Precharge Command to interrupt a burst cycle and
close the active bank, or using the Burst Stop Com-
mand to terminate the existing burst operation but
leave the bank open for future Read or Write Com-
mands to the same page of the active bank. When
interrupting a burst with another Read or Write Com-
mand care must be taken to avoid I/O contention.
The Burst Stop Command, however, has the fewest
restrictions making it the easiest method to use
when terminating a burst operation before it has
been completed. If a Burst Stop command is issued
during a burst write operation, then any residual data
from the burst write cycle will be ignored. Data that
is presented on the I/O pins before the Burst Stop
Command is registered will be written to the
memory.
Bank Selection by Address Bits:
A10 BA0 BA1
000
001
010
011
1 XX
Bank 0
Bank 1
Bank 2
Bank 3
all Banks
V54C365164VD(L) Rev. 1.3 September 2001
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet V54C365164VD.PDF ] | |
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