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Número de pieza | V54C3128404VE | |
Descripción | (V54C3xxxx4VE) 64Mbit SDRAM | |
Fabricantes | ProMOS Technologies | |
Logotipo | ||
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V54C365(16/80/40)4VE
64Mbit SDRAM
3.3 VOLT, TSOP II / FBGA
4M X 16, 8M X 8, 16M X 4
System Frequency (fCK)
Clock Cycle Time (tCK3)
Clock Access Time (tAC3) CAS Latency = 3
Clock Access Time (tAC2) CAS Latency = 2
6
166 MHz
6 ns
5.4 ns
5.4 ns
7PC
143 MHz
7 ns
5.4 ns
5.4 ns
7
143 MHz
7 ns
5.4 ns
6 ns
8PC
125 MHz
8 ns
6 ns
6 ns
Features
■ 4 banks x 1Mbit x 16 organization
■ 4 banks x 2Mbit x 8 organization
■ 4 banks x 4Mbit x 4 organization
■ High speed data transfer rates up to 166 MHz
■ Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
■ Single Pulsed RAS Interface
■ Data Mask for Read/Write Control
■ Four Banks controlled by BA0 & BA1
■ Programmable CAS Latency: 2, 3
■ Programmable Wrap Sequence: Sequential or
Interleave
■ Programmable Burst Length:
1, 2, 4, 8, and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
■ Multiple Burst Read with Single Write Operation
■ Automatic and Controlled Precharge Command
■ Random Column Address every CLK (1-N Rule)
■ Power Down Mode
■ Auto Refresh and Self Refresh
■ Refresh Interval: 4096 cycles/64 ms
■ Available in 54-ball FBGA, 60-ball FBGA, and
54-Pin TSOPII
■ LVTTL Interface
■ Single +3.3 V ±0.3 V Power Supply
Description
The V54C365(16/80/40)4VE is a four bank Syn-
chronous DRAM organized as 4 banks x 1Mbit x 16,
4 banks x 2Mbit x 8, or 4 banks x 4Mbit x 4. The
V54C365(16/80/40)4VE achieves high speed data
transfer rates up to 166 MHz by employing a chip
architecture that prefetches multiple bits and then
synchronizes the output data to a system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
C/S/T
•
6
•
Access Time (ns)
7PC
•
7
•
8PC
•
Power
Std.
•
L
•
Temperature
Mark
Blank
V54C365(16/80/40)4VE Rev. 1.4 March 2006
1
1 page www.DataSheet4U.com
ProMOS TECHNOLOGIES
V54C365(16/80/40)4VE
64Mb SDRAM Pin Assignment
(54-Pin TSOP-II)
Description Pkg.
TSOP-II
T/I
Pin Count
54
x16 Configuration
Top View
VCC
I/O1
VCCQ
I/O2
I/O3
VSSQ
I/O4
I/O5
VCCQ
I/O6
I/O7
VSSQ
I/O8
VCC
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 VSS
53 I/O16
52 VSSQ
51 I/O15
50 I/O14
49 VCCQ
48 I/O13
47 I/O12
46 VSSQ
45 I/O11
44 I/O10
43 VCCQ
42 I/O9
41 VSS
40 NC
39 UDQM
38 CLK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 VSS
Pin Names
CLK
CKE
CS
RAS
CAS
WE
A0–A11
BA0, BA1
I/O1–I/O16
LDQM, UDQM
VCC
VSS
VCCQ
VSSQ
NC
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
Data Input/Output
Data Mask
Power (+3.3V)
Ground
Power for I/O’s (+3.3V)
Ground for I/O’s
Not connected
V54C365(16/80/40)4VE Rev. 1.4 March 2006
5
5 Page www.DataSheet4U.com
ProMOS TECHNOLOGIES
V54C365(16/80/40)4VE
Signal Pin Description
Pin Type
CLK Input
CKE
Input
CS Input
RAS, CAS Input
WE
A0 - A11 Input
Signal Polarity
Function
Pulse
Positive The system clock input. All of the SDRAM inputs are sampled on the rising edge of the
Edge clock.
Level Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
initiates either the Power Down mode or the Self Refresh mode.
Pulse
Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
Level
— During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)
when sampled at the rising clock edge.CAn depends from the SDRAM organization:
• 16M x 4 SDRAM CA0–CA9.
• 8M x 8 SDRAM CA0–CA8.
• 4M x 16 SDRAM CA0–CA7.
BA0,
BA1
DQx
LDQM
UDQM
Input
Input
Output
Input
VCC, VSS Supply
VCCQ
VSSQ
Supply
Level
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will BA0 and BA1 are
used to define which bank to precharge.
— Selects which bank is to be active.
Level
— Data Input/Output pins operate in the same manner as on conventional DRAMs.
Pulse
Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sam-
pled high. In Read mode, DQM has a latency of two clock cycles and controls the output
buffers like an output enable. In Write mode, DQM has a latency of zero and operates as
a word mask by allowing input data to be written if it is low but blocks the write operation
if DQM is high.
Power and ground for the input buffers and the core logic.
— — Isolated power supply and ground for the output buffers to provide improved noise
immunity.
V54C365(16/80/40)4VE Rev. 1.4 March 2006
11
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet V54C3128404VE.PDF ] |
Número de pieza | Descripción | Fabricantes |
V54C3128404VBGA | 128Mbit SDRAM 3.3 VOLT/ BGA PACKAGE | Mosel Vitelic Corp |
V54C3128404VE | (V54C3xxxx4VE) 64Mbit SDRAM | ProMOS Technologies |
V54C3128404VS | 128Mbit SDRAM 3.3 VOLT/ TSOP II / SOC PACKAGE 8M X 16/ 16M X 8/ 32M X 4 | Mosel Vitelic Corp |
V54C3128404VT | 128Mbit SDRAM 3.3 VOLT/ TSOP II / SOC PACKAGE 8M X 16/ 16M X 8/ 32M X 4 | Mosel Vitelic Corp |
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