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PDF GD16585 Data sheet ( Hoja de datos )

Número de pieza GD16585
Descripción Transmitter MUX
Fabricantes Giga 
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10 Gbit/s
Transmitter MUX
with Re-timing
GD16585
Preliminary
General Description
Features
GD16585 is a 9.95328 Gbit/s transmitter
chip for use in SDH STM-64 and SONET
OC-192 optical communication systems.
GD16585 integrates all the main func-
tions of the transmitter, which is clock
generation, PLL circuits and multiplexer
in a single monolithic IC. Hence only an
external loop filter and a VCXO are
required.
The main functions of GD16585 are
shown in the figure below. The clock
generation is made on-chip by a low
noise and tuneable 10 GHz VCO. The
VCO frequency is controlled by the PLL
with an external loop filter, allowing the
user to control the loop characteristic.
The clock synchronisation is controlled
by the Phase and Frequency Detector
with a 155 MHz or 622 MHz reference
clock input.
GD16585 multiplexes a 16 bit parallel
622 Mbit/s interface into a serial
9.9553 Gbit/s data stream.
The timing between the input data and
the on-chip clock system are controlled
by a second Phase and Frequency De-
tector (PFCX). It compares the input data
clock with the on-chip load clock. The
output of the PFCX is the phase and fre-
quency control of the external VCXO
reference clock.
The output of the MUX stage is retimed
by the 10 GHz clock and the output
driver is a Current Mode Logic (CML)
output with internal 50 termination re-
sistors.
The 16 bit wide parallel input interface is
LVDS compatible with a 2 × 50 internal
load termination.
GD16585 is manufactured in a Silicon Bi-
polar process.
GD16585 uses a -5.2 V supply voltage
and +3.3 V supply for interfacing LVDS.
The power dissipation is 2.2 W, typical.
GD16585 is delivered in an 132 leads
ceramic Ball Grid Array (BGA). The size
of the package is 13 × 13 mm.
DI0
DIN0
Parallel
Input Data
DI15
DIN15
SEL1
SEL2
CKOUT
CKOUTN
CKI
CKIN
16:1
Multiplexer
FF
Phase
Selector
PFCX
Timing
Control
VCO
PCTLX SGNX
VCTL
VCUR
OUT
OUTN
Phase
Frequency
Detector
NLDET
PCTL
PHIGH
PLOW
TCK
SEL3 REFCK/N VCC VDD VDDO VDDA VEE
l On-chip low noise VCO with a wide
tuning range.
l Automated capture of the VCO
frequency by a true phase and
frequency detector.
l Retiming of MUX stage output with
10 GHz clock.
l Clock failure detection NLDET.
l Phase nulling circuit for easy
interfacing with the system ASIC.
l 16:1 MUX with differential 622 Mbit/s
LVDS data inputs.
l CML data input with 50 internal
load termination.
l LVDS compatible data and clock
inputs with 100 internal load termi-
nation.
l 622 MHz clock output for counter
clocking.
l 155 MHz or 622 MHz reference clock
input (selectable).
l Dual supply operation: -5.2 V and
+3.3 V
l Low power dissipation: 2.2 W (typ.).
l Silicon Bipolar process.
l 132 leads ceramic BGA 13 × 13 mm
package.
l Available in two versions:
– GD16585 for 10 Gbit/s
– GD16589 for 10.66 Gbit/s
Applications
l Telecommunication systems:
– SDH STM-64
– SONET OC-192.
l Fibre optic test equipment.

1 page




GD16585 pdf
10 Gbit/s Output Interface
www.DataSheet4U.com
GD16585
0V
50
OUT
OUTN
50MSL
-5.2V
Figure 3. 10 Gbit/s Outputs (OUT/OUTN), DC Coupled.
GD16585
0V
50
OUT
100nF
OUTN
50MSL
-5.2V
Figure 4. 10 Gbit/s Outputs (OUT/OUTN), AC Coupled.
Driver
50
Driver
50
Data Sheet Rev. 04
GD16585
Page 5 of 13

5 Page





GD16585 arduino
www.DAataCSheCet4hUa.cormacteristics, Timing Control to System ASIC.
TCASE = 0 °C to 70 °C, VEE = -5.2 V.
GD16585
DI0
DI15
16 bit @ 622 Mbit/s
System ASIC
CKI
CKIN
REFCK
REFCKN
PCTLX
VCXO
-5.2 V
Figure 9. Phase Nulling Circuit.
CKI
DI0-15
tS,RF
tH,RF
Figure 10. Timing relation between input data and clock.
Symbol:
tS,RF
tH,RF
Characteristic:
DI0-15 setup before CKI
DI0-15 hold from CKI
Conditions:
VEE = -5.2V, TC=70°, SEL3 = 1
VEE = -5.2V, TC=70°, SEL3 = 1
MIN.:
TYP.:
TBD
TBD
MAX.:
UNIT:
ps
ps
Data Sheet Rev. 04
GD16585
Page 11 of 13

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