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PDF PC8374T Data sheet ( Hoja de datos )

Número de pieza PC8374T
Descripción SafeKeeper Desktop Trustedl/O
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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PRODUCT BRIEF
August 2004
Revision 1.1
PC8374T
SafeKeeperDesktop TrustedI/O
General Description
The National Semiconductor PC8374T Advanced I/O prod-
uct is a member of the PC837x SuperI/O family. All PC837x
devices are highly integrated and are pin and software com-
patible, thus providing drop-in interchangeability and en-
abling a variety of assembly options using only a single
motherboard and BIOS.
PC8374T integration allows for a reduced system board size
and saves on total system cost.
The PC8374T includes legacy SuperI/O functions, Trusted
Platform Module (TPM), system glue functions, health mon-
itoring and control, commonly used functions such as GPIO,
and ACPI-compliant Power Management support.
The Trusted Platform Module provides a solution for PC se-
curity, based on the TCG standard. The complete security
solution includes hardware, software, and firmware.
The PC8374T integrates miscellaneous analog and digital
system glue functions to reduce the number of discrete
components required. The host communicates with the
functions integrated in the PC8374T through an LPC Bus
Interface.
The PC8374T supports both I/O and memory mapping of
module registers and enables building legacy-free systems.
Outstanding Features
TCG 1.1b based Trusted Platform Module (TPM)
Integrated non-volatile secure storage
Hardware and software protection schemes
Tamper resistance schemes
Pin compatible to integrated TPM 1.2 device
Legacy modules: Parallel Port, Floppy Disk Controller
(FDC), two Serial Ports, Serial InfraRed Port and a Key-
board and Mouse Controller (KBC)
Glue functions to complement the South Bridge func-
tionality
System health support, including SensorPathsensor
interface, and fan monitor and control
VSB3-powered Power Management with 19 wake-up
sources
Controls three LED indicators
16 GPIO pins with a variety of wake-up options
I/O-mapped and memory-mapped registers
128-pin PQFP package
PC8374T System Block Diagram
South Bridge
System
BIOS
VBAT
SMBus I/F
LPC Bus
PC8374T
TPM
Power Management
SuperI/O
Serial Interface x 2
Parallel Port Interface
Floppy Drive Interface
PS/2 Interfaces
KBC Ports
Infrared Interface
GPIO
Wake-Up
Events
Physical
Presence
Reset
Logic
LEDs
SensorPathTM I/F
LMxx Sensors
Tacho
Power
Supply
PWM
DDrDvrrvv
National Semiconductor and TRI-STATEare registered trademarks of National Semiconductor Corporation.
SensorPathand SafeKeeperare trademarks of National Semiconductor Corporation.
All other brand or product names are trademarks or registered trademarks of their respective holders.
© 2004 National Semiconductor Corporation
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PC8374T pdf
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1.0 Signal/Pin Connection and Description
1.1 CONNECTION DIAGRAM
CLOCKI14
HD_LED
PRIMARY_HD
SECONDARY_HD
SCSI
REF5V
VSB5
REF5V_STBY
PCIRST_OUT
PCIRST_OUT2/GPIOE12
GPIOE13
VSB3
BKFD_CUT
VSS
LATCHED_BF_CUT
GPIOE17
PS_ON
PWRGD_PS
CPU_PRESENT
PWRGD_3V
SLP_S3
SLP_S5
SMB1_SCL
HMSCL/SMB2_SCL
SMB1_SDA
HMSDA/SMB2_SDA
IOPA1/CLOCKI32/GPIO15
RSMRST
VSB3
GRN_LED
YLW_LED
VSS
VCORF
VBAT
SIOPME
GPIOE16
IOPA0/GPIOE14
VCORF2
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
PC8374T
128-Pin PQFP
(Top View)
38 PD6
37 PD7
36 ACK
35 BUSY_WAIT
34 PE
33 SLCT
32 RI1
31 VDD3
30 DTR_BOUT1/XOR_OUT/BADDR
29 VSS
28 CTS1
27 SOUT1/TEST
26 RTS1/TRIS
25 SIN1
24 DSR1
23 DCD1
22 DENSEL
21 DRATE0
20 INDEX
19 MTR0
18 DR0
17 DIR
16 STEP
15 WDATA
14 WGATE
13 TRK0
12 WP
11 RDATA
10 HDSEL
9 DSKCHG
8 VSS
7 KBRST
6 VDD3
5 GA20
4 KBDAT
3 KBCLK
2 MDAT
1 MCLK
Revision 1.1
Plastic Quad Flatpack (PQFP), JEDEC
Order Number PC8374T0xxx/VLA
Package Number VLA128A
5
Note: ’xxx’ stands for the following Keyboard
Controller Microcodes:
IBW - for AMI
IBU - for Intel
IBM - for IBM
ICG - for Dell
ICK - for Phoenix
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PC8374T arduino
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1.0 Signal/Pin Connection and Description (Continued)
Signal
SOUT1
SOUT2
Pin(s) I/O Buffer Type Power Well
Description
27 O
120 or O
122
O4/8
O4/8
VDD3
VDD3
Serial Output. Sends composite serial data to the
communications link (peripheral device, modem or other data
transfer device). These signals are set active high after a system
reset.
1.4.3 InfraRed Port
Signal
IRRX
IRTX
Pin(s) I/O Buffer Type Power Well
Description
127 or
120
128 or
118
I
O
INTS
O6/12
VDD3 InfraRed Receive. InfraRed serial input data.
VDD3 InfraRed Transmit. InfraRed serial output data.
1.4.4 Parallel Port
Signal Pin(s) I/O Buffer Type Power Well
Description
ACK
36
AFD_DSTRB 50
BUSY_WAIT 35
ERR
INIT
45
48
PD7-0
37-44
PE 34
SLCT
33
SLIN_ASTRB 47
I INT
O OD14, O14/14
I INT
I INT
O OD14, O14/14
I/O INT/O14/14
I INT
I INT
O OD14, O14/14
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
Acknowledge. Pulsed low by the printer to indicate that it has
received data from the parallel port.
AFD - Automatic Feed. When low, instructs the printer to
automatically feed a line after printing each line. This pin is in
TRI-STATE after a 0 is loaded into the corresponding control
register bit. An external 4.7 Kpull-up resistor must be
connected to this pin.
DSTRB - Data Strobe (EPP). Active low; used in EPP mode
to denote a data cycle. When the cycle is aborted, DSTRB
becomes inactive (high).
Busy. Set high by the printer when it cannot accept another
character.
Wait. In EPP mode, the parallel port device uses this active
low signal to extend its access cycle.
Error. Set active low by the printer when it detects an error.
Initialize. When low, initializes the printer. This signal is in
TRI-STATE after a 1 is loaded into the corresponding control
register bit. An external 4.7 Kpull-up resistor must be
connected to this pin.
Parallel Port Data. Transfers data to and from the peripheral
data bus and the appropriate parallel port data register. These
signals have a high current drive capability.
Paper End. Set high by the printer when it is out of paper.
This pin has an internal weak pull-up or pull-down resistor.
Select. Set active high by the printer when the printer is
selected.
SLIN - Select Input. When low, selects the printer. This signal
is in TRI-STATE after a 0 is loaded into the corresponding
control register bit. An external 4.7 Kpull-up resistor must be
connected to this pin.
ASTRB - Address Strobe (EPP). Active low, used in EPP
mode to denote an address cycle. When the cycle is aborted,
ASTRB becomes inactive (high).
Revision 1.1
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