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PDF DS0056 Data sheet ( Hoja de datos )
| Número de pieza | DS0056 | |
| Descripción | Dual High-Speed MOS Driver | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de DS0056 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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October 2000
DS0026
Dual High-Speed MOS Driver
General Description
DS0026 is a low cost monolithic high speed two phase MOS
clock driver and interface circuit. Unique circuit design pro-
vides both very high speed operation and the ability to drive
large capacitive loads. The device accepts standard TTL
outputs and converts them to MOS logic levels. The device
may be driven from standard 54/74 series and 54S/74S
series gates and flip-flops or from drivers such as the
DS8830 or DM7440. The DS0026 is intended for applica-
tions in which the output pulse width is logically controlled;
i.e., the output pulse width is equal to the input pulse width.
The DS0026 is designed to fulfill a wide variety of MOS
interface requirements. Information on the correct usage of
the DS0026 in these as well as other systems is included in
the application note AN-76.
Features
n Fast rise and fall times — 20 ns 1000 pF load
n High output swing — 20V
n High output current drive — ±1.5 amps
n TTL compatible inputs
n High rep rate — 5 to 10 MHz depending on power
dissipation
n Low power consumption in MOS “0” state — 2 mW
n Drives to 0.4V of GND for RAM address drive
Connection Diagram (Top View)
Dual-In-Line Package
DS005853-2
Order Number DS0026CN
See NS Package Number N08E
© 2000 National Semiconductor Corporation DS005853
www.national.com
1 page  
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AC Test Circuits and Switching Time Waveforms
DS005853-12
FIGURE 1.
DS005853-13
DS005853-15
DS005853-14
FIGURE 2.
Typical Applications
AC Coupled MOS Clock Driver
DS005853-16
DC Coupled RAM Memory Address or Precharge
Driver (Positive Supply Only)
DS005853-17
Application Hints
DRIVING THE MM5262 WITH THE
DS0026 CLOCK DRIVER
The clock signals for the MM5262 have three requirements
which have the potential of generating problems for the user.
These requirements, high speed, large voltage swing and
large capacitive loads, combine to provide ample opportunity
for inductive ringing on clock lines, coupling clock signals to
other clocks and/or inputs and outputs and generating noise
on the power supplies. All of these problems have the po-
tential of causing the memory system to malfunction. Rec-
ognizing the source and potential of these problems early in
the design of a memory system is the most critical step. The
object here is to point out the source of these problems and
give a quantitative feel for their magnitude.
Line ringing comes from the fact that at a high enough
frequency any line must be considered as a transmission
line with distributed inductance and capacitance. To see how
much ringing can be tolerated we must examine the clock
voltage specification. Figure 3 shows the clock specification,
in diagram form, with idealized ringing sketched in. The
ringing of the clock about the VSS level is particularly critical.
If the VSS − 1 VOH is not maintained, at all times, the
information stored in the memory could be altered. Referring
to Figure 1, if the threshold voltage of a transistor were
−1.3V, the clock going to VSS − 1 would mean that all the
devices, whose gates are tied to that clock, would be only
300 mV from turning on. The internal circuitry needs this
noise margin and from the functional description of the RAM
it is easy to see that turning a clock on at the wrong time can
have disastrous results.
5 www.national.com
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet DS0056.PDF ] | |
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