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PDF M5M5117FP Data sheet ( Hoja de datos )
| Número de pieza | M5M5117FP | |
| Descripción | 16K-Bit CMOS Static RAM | |
| Fabricantes | Mitsubishi Electric | |
| Logotipo |  |
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MITSUBISHI LSI.
MsMsI17FP, -15
16384-BIT (2048-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5117FP series of 2048-word by 8-bit asynchro-
nous silicon gate CMOS static RAM operates on a single 5V
power supply and is designed for easy use in applications
requiring battery backup.
A chip select input, S, is available to provide the mini-
mum standby current with battery back-up while an output
enable input, OE, enables high-speed memory access.
The series features pin compatibility with the M5L2716K
16K EPROM and M58725P 16K static RAM, and it is
packaged in a small 24-pin plastic OIL flat package.
FEATURES
Type name
Access time
(max)
M5M5117FP-15 150ns
M5M5117FP
200ns
DE access
time
(max)
80ns
lOOns
Current consumption
Active
(max)
Stand-by
(max)
SOmA
15iIA
• Single 5V power supply.
• External clock and refresh operation not required.
• Data can be held with 2V supply voltage.
• All inputs, and outputs are directly TTL compatible.
• All outputs are 3-state with OR-tie capability.
• Easy expansion of memory capacity with chip select
signal.
• Common input/output for data pins.
• Pin compatibility with M5L2716K 16K EPROM and
M58725P 16K static RAM.
APPLICATIONS
Battery drive, small-capacity memory units with battery
back-up
PIN CONFIGURATION (TOP VIEW)
ADDRESS A4
INPUTS AJ
Az
Al
Ao
IDATA DO,
INPUTS/ DOz
OUTPUTS DOJ
(OV) GND
Vee (5V)
I23 ~ A, ADDRESS
I22 ~ A, INPUTS
21 ~ Iii ~~\Jf CONTROL
2D ~ DE ?NUpTI'TUT ENABLE
19 ~ A 10 ADDRESS INPUT
CHIP SELECT
INPUT
DATA
INPUTSI
OUTPUTS
Outline 24P2W
FUNCTION
The M5M5117FP series has a 2048-word by 8-bit configura-
tion. It operates on a single 5V supply and its inputs/
outputs are directly TTL compatible. Its completely static
circuitry obviates the need for external clock and refresh
operations and makes it very easy to use.
The data of the DO pin are written when the address is
designated by address signals Ao - AIO , the Ssignals turns
low-level, and the W signal is set low.
When for the reading operation the W signal is set high,
the Sand OE signals are set low, pin DO is set to the output
mode and the address is designated by signals Ao - AIO ,
the data of the designated address are output to pin DO.
BLOCK DIAGRAM
ADDRESS INPUTS
A,
As
2048-WORD
X 8-BIT RAM
(128 ROWS X 128
COLUMNS)
DATA
I NPUTS/OUTPUTS
WRITE CONTROL INPUT Vi
CHIP SELECT INPU" S 18
OUTPUT ENABLE INPUT DE 20
L.._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
4-18
-• -- MITSUBISHI
;"ELECTRIC
1 page  
MITSUBISHI LSls
MsMsI17FP, -15
16384-BIT (2048-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle (8 control)
lew
w
DO,-DOg
(DATA IN)
DO,-DOg
(DATA OUT)
OE = LOW LEVEL
Note 4 Test conditions
Input pulse level: 0.4 -- 2.4V
Input pulse risetime and fall time lOns
Load: lTTL. C,L ~ 100pF
Reference level: 1.SV
tsu (Si
lw (W)
Note 5: Hatching indicates the don't care inputs.
6 Writing is performed while Sand Ware in the low-level
overlap period.
7: The output is kept in the high-impedance state when Iii
Sfalls simultaneously with, or before, the falls.
8' A reverse phase signal should not be supplied when DO
is in the output mode.
POWER-DOWN CHARACTERISTICS
Vee
VCC{PDI
'.MITSUBISHI
4-22
"'ELECTRIC
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet M5M5117FP.PDF ] | |
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