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PDF D72103A Data sheet ( Hoja de datos )
| Número de pieza | D72103A | |
| Descripción | UPD72103A | |
| Fabricantes | NEC | |
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µPD72103A
HDLC CONTROLLER
© 1997
µPD72103A
Document No. S10766EJ9V0UM00 (9th edition)
Date Published March 1997 N CP(N)
Printed in Japan
1 page  
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Legend
Data representation weight : High-order digits are indicated at left and low-order digits
at right.
Active low representation : xxx (pin or signal name is overlined) or xxxB (“B” is added
after signal and pin names)
Memory map address
: High order at low stage and low order at high stage (address
0H)
Note
: Explanation of Note in the text
Caution
: Item deserving extra attention
Remark
: Supplementary explanation to the text
Number representation : Decimal number is xxxx
Hexadecimal number is xxxxH
Appendix C uses the following abbreviations for reference documentation.
Data sheet
User’s manual
Application note
→ DS
→ UM
→ AN
Related Documentation
Document name
µPD72103A
Data Sheet
S10189JNote
User’s Manual
This manual
Application Note
—
The corresponding application note for this manual is the µPD72103 APPLICATION
NOTE (IEA-713Note). In this application note, all references to the µPD72103 should be
understood as referring to the µPD72103A.
Note This document number is that of the Japanese version.
5 Page 
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CHAPTER 1 GENERAL
1.2 Block Diagram
Corresponding sections of this manual are indicated in the bubbles.
D0-D7
A16D8-
A23D15
A0-A15
CS
IORD
IOWR
UBE
AEN
ASTB
HLDRQ
HLDAK
MRD
MWR
READY
CRQ
INT
CLRINT
B/W
TEST
VDD
GND
RESET
CLK
Bus
interface
Chapter 2
All chapters
Internal controller
Tx
FIFO
2.3.1
Internal buses
2.3.1
DMAC
Rx
FIFO
2.2
3.3
Transmitter
TxC
TxD
Receiver
GI1
GI2
GO1
GO2
GO3
RxC
RxD
3.4
2
11 Page | ||
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| PDF Descargar | [ Datasheet D72103A.PDF ] | |
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