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PDF INTEL386DX Data sheet ( Hoja de datos )

Número de pieza INTEL386DX
Descripción 32-bit Chmos Microprocessor
Fabricantes Intel Corporation 
Logotipo Intel Corporation Logotipo



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Intel386TM DX MICROPROCESSOR
32-BIT CHMOS MICROPROCESSOR
WITH INTEGRATED MEMORY MANAGEMENT
Y Flexible 32-Bit Microprocessor
8 16 32-Bit Data Types
8 General Purpose 32-Bit Registers
Y Very Large Address Space
4 Gigabyte Physical
64 Terabyte Virtual
4 Gigabyte Maximum Segment Size
Y Integrated Memory Management Unit
Virtual Memory Support
Optional On-Chip Paging
4 Levels of Protection
Fully Compatible with 80286
Y Object Code Compatible with All 8086
Family Microprocessors
Y Virtual 8086 Mode Allows Running of
8086 Software in a Protected and
Paged System
Y Hardware Debugging Support
Y Optimized for System Performance
Pipelined Instruction Execution
On-Chip Address Translation Caches
20 25 and 33 MHz Clock
40 50 and 66 Megabytes Sec Bus
Bandwidth
Y Numerics Support via Intel387TM DX
Math Coprocessor
Y Complete System Development
Support
Software C PL M Assembler
System Generation Tools
Debuggers PSCOPE ICETM-386
Y High Speed CHMOS IV Technology
Y 132 Pin Grid Array Package
Y 132 Pin Plastic Quad Flat Package
(See Packaging Specification Order 231369)
The Intel386 DX Microprocessor is an entry-level 32-bit microprocessor designed for single-user applications
and operating systems such as MS-DOS and Windows The 32-bit registers and data paths support 32-bit
addresses and data types The processor addresses up to four gigabytes of physical memory and 64 terabytes
(2 46) of virtual memory The integrated memory management and protection architecture includes address
translation registers multitasking hardware and a protection mechanism to support operating systems Instruc-
tion pipelining on-chip address translation ensure short average instruction execution times and maximum
system throughput
The Intel386 DX CPU offers new testability and debugging features Testability features include a self-test and
direct access to the page translation cache Four new breakpoint registers provide breakpoint traps on code
execution or data accesses for powerful debugging of even ROM-based systems
Object-code compatibility with all 8086 family members (8086 8088 80186 80188 80286) means the
Intel386 DX offers immediate access to the world’s largest microprocessor software base
Intel386TM DX Pipelined 32-Bit Microarchitecture
Intel386TM DX and Intel387TM DX are Trademarks of Intel Corporation
MS-DOS and Windows are Trademarks of MICROSOFT Corporation
231630 – 49
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
December 1995
Order Number 231630-011

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INTEL386DX pdf
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Intel386TM DX MICROPROCESSOR
1 PIN ASSIGNMENT
The Intel386 DX pinout as viewed from the top side
of the component is shown by Figure 1-1 Its pinout
as viewed from the Pin side of the component is
Figure 1-2
VCC and GND connections must be made to multi-
ple VCC and VSS (GND) pins Each VCC and VSS
must be connected to the appropriate voltage level
The circuit board should include VCC and GND
planes for power distribution and all VCC and VSS
pins must be connected to the appropriate plane
NOTE
Pins identified as ‘‘N C ’’ should remain completely
unconnected
231630 – 33
231630 – 34
Figure 1-1 Intel386TM DX PGA
Pinout View from Top Side
Figure 1-2 Intel386TM DX PGA
Pinout View from Pin Side
Table 1-1 Intel386TM DX PGA Pinout Functional Grouping
Signal Pin
A2 C4
A3 A3
A4 B3
A5 B2
A6 C3
A7 C2
A8 C1
A9 D3
A10 D2
A11 D1
A12 E3
A13 E2
A14 E1
A15 F1
A16 G1
A17 H1
A18 H2
A19 H3
A20 J1
A21 K1
A22 K2
A23 L1
Signal Pin
A24
A25
A26
A27
A28
A29
A30
A31
ADS
BE0
BE1
BE2
BE3
BS16
BUSY
CLK2
D0
D1
D2
D3
D4
D5
L2
K3
M1
N1
L3
M2
P1
N2
E14
E12
C13
B13
A13
C14
B9
F12
H12
H13
H14
J14
K14
K13
Signal Pin
D6 L14
D7 K12
D8 L13
D9 N14
D10 M12
D11 N13
D12 N12
D13 P13
D14 P12
D15 M11
D16 N11
D17 N10
D18 P11
D19 P10
D20 M9
D21 N9
D22 P9
D23 N8
D24 P7
D25 N6
D26 P5
D27 N5
Signal Pin
D28
D29
D30
D31
DC
ERROR
HLDA
HOLD
INTR
LOCK
M IO
NA
NMI
PEREQ
READY
RESET
VCC
M6
P4
P3
M5
A11
A8
M14
D14
B7
C10
A12
D13
B8
C8
G13
C9
A1
A5
A7
A10
A14
C5
Signal Pin
VCC C12
D12
G2
G3
G12
G14
L12
M3
M7
M13
N4
N7
P2
P8
VSS A2
A6
A9
B1
B5
B11
B14
C11
Signal Pin
VSS
WR
NC
F2
F3
F14
J2
J3
J12
J13
M4
M8
M10
N3
P6
P14
B10
A4
B4
B6
B12
C6
C7
E13
F13
5

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INTEL386DX arduino
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Intel386TM DX MICROPROCESSOR
OF (Overflow Flag bit 11)
OF is set if the operation resulted in a signed
overflow Signed overflow occurs when the
operation resulted in carry borrow into the
sign bit (high-order bit) of the result but did
not result in a carry borrow out of the high-
order bit or vice-versa For 8 16 32 bit oper-
ations OF is set according to overflow at bit
7 15 31 respectively
DF (Direction Flag bit 10)
DF defines whether ESI and or EDI registers
postdecrement or postincrement during the
string instructions Postincrement occurs if
DF is reset Postdecrement occurs if DF is
set
IF (INTR Enable Flag bit 9)
The IF flag when set allows recognition of
external interrupts signalled on the INTR pin
When IF is reset external interrupts signalled
on the INTR are not recognized IOPL indi-
cates the maximum CPL value allowing alter-
ation of the IF bit when new values are
popped into EFLAGS or FLAGS
TF (Trap Enable Flag bit 8)
TF controls the generation of exception 1
trap when single-stepping through code
When TF is set the Intel386 DX generates an
exception 1 trap after the next instruction is
executed When TF is reset exception 1
traps occur only as a function of the break-
point addresses loaded into debug registers
DR0 – DR3
SF (Sign Flag bit 7)
SF is set if the high-order bit of the result is
set it is reset otherwise For 8- 16- 32-bit
operations SF reflects the state of bit 7 15
31 respectively
ZF (Zero Flag bit 6)
ZF is set if all bits of the result are 0 Other-
wise it is reset
AF (Auxiliary Carry Flag bit 4)
The Auxiliary Flag is used to simplify the addi-
tion and subtraction of packed BCD quanti-
ties AF is set if the operation resulted in a
carry out of bit 3 (addition) or a borrow into bit
3 (subtraction) Otherwise AF is reset AF is
affected by carry out of or borrow into bit 3
only regardless of overall operand length 8
16 or 32 bits
PF (Parity Flags bit 2)
PF is set if the low-order eight bits of the op-
eration contains an even number of ‘‘1’s’’
(even parity) PF is reset if the low-order eight
bits have odd parity PF is a function of only
the low-order eight bits regardless of oper-
and size
CF (Carry Flag bit 0)
CF is set if the operation resulted in a carry
out of (addition) or a borrow into (subtraction)
the high-order bit Otherwise CF is reset For
8- 16- or 32-bit operations CF is set accord-
ing to carry borrow at bit 7 15 or 31 respec-
tively
Note in these descriptions ‘‘set’’ means ‘‘set to 1 ’’
and ‘‘reset’’ means ‘‘reset to 0 ’’
2 3 4 Segment Registers
Six 16-bit segment registers hold segment selector
values identifying the currently addressable memory
segments Segment registers are shown in Figure 2-
4 In Protected Mode each segment may range in
size from one byte up to the entire linear and physi-
SEGMENT
REGISTERS
V
15
Selector
Selector
Selector
Selector
Selector
Selector
WV
DESCRIPTOR REGISTERS (LOADED AUTOMATICALLY)
Other
Segment
0 Physical Base Address Segment Limit Attributes from Descriptor
CS –
SS –
DS –
ES –
FS –
GS –
W
Figure 2-4 Intel386TM DX Segment Registers and Associated Descriptor Registers
11

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