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PDF LC876124A Data sheet ( Hoja de datos )
| Número de pieza | LC876124A | |
| Descripción | (LC876116A - LC876132A) 8-Bit Single Chip Microcontroller | |
| Fabricantes | Sanyo Electric | |
| Logotipo |  |
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Ordering number : ENN*7373
CMOS IC
LC876132A/24A/16A
8 bit Single Chip Microcontroller with
32K/24K/16K-Byte ROM and 768-Byte RAM on Chip
Preliminary
Overview
The LC876132A/24A/16A are 8 bit single chip
microcontrollers with the following on-chip functional
blocks :
• CPU: operable at a minimum bus cycle time of 100ns
• On-chip ROM Maximum Capacity :
LC876132A
32K bytes
LC876124A
24K bytes
LC876116A
16K bytes
• On-chip RAM: 768 bytes
• VFD automatic display controller / driver
• 16 bit timer / counter
(can be divided into two 8 bit timers)
• 16 bit timer / PWM
(can be divided into two 8 bit timers)
• System clock divider function
• Synchronous serial I/O port
(with automatic block transmit / receive function)
• Asynchronous / synchronous serial I/O port
• 10-channel × 8-bit AD converter
• 13-source 10-vectored interrupt system
Package Dimensions
unit: mm
3174A
[ LC876132A/24A/16A ]
All of the above functions are fabricated on a single chip.
Ver.1.01
70201
22504 TN IM NO No.7373-1/17
1 page  
www.DataSheet4U.com
System Block Diagram
LC876132A/24A/16A
Interrupt Control
Stand-by Control
CF
MRC
RC
SIO0
SIO1
Timer 0
Timer 1
VFD Controller
INT0 - 3
Noise Rejection
Filter
Bus Interface
Port 0
Port 1
Port 7
ADC
IR PLA
ROM
PC
ACC
B Register
C Register
ALU
PSW
RAR
RAM
Stack Pointer
WatchDog Timer
No.7373-5/17
5 Page 
www.DataSheet4U.com
LC876132A/24A/16A
Serial Input / Output Characteristics / Ta=-30°C to +70°C, VSS1=0V
Parameter
Symbol
Pins
Conditions
VDD [V]
min
[Serial clock]
[Input clock]
Cycle time
tSCK(1)
SCK0(P12)
Refer to figure 5
4/3
Low level pulse
width
tSCKL(1)
tSCKLA(1)
4.5 to 5.5
2/3
2/3
High level pulse
width
tSCKH(1)
tSCKHA(1)
2/3
3
Cycle time
tSCK(2)
SCK1(P15)
Refer to figure 5
2
Low level pulse
width
High level pulse
width
tSCKL(2)
tSCKH(2)
4.5 to 5.5
1
1
[Output clock]
Cycle time
Low level pulse
width
tSCK(3)
tSCKL(3)
tSCKLA(2)
SCK0(P12)
•CMOS output option
•Refer to figure 5
4.5 to 5.5
4/3
High level pulse
width
tSCKH(3)
tSCKHA(2)
Cycle time
Low level pulse
width
High level pulse
width
tSCK(4)
tSCKL(4)
tSCKH(4)
SCK1(P15)
•CMOS output option
•Refer to figure 5
4.5 to 5.5
2
[Serial input]
Data set-up time
Data hold time
tsDI
thDI
[Serial output]
SI0(P11), SI1(P14),
SB0(P11), SB1(P14)
•Measured with respect
to SI0CLK leading
edge.
•Refer to figure 5
4.5 to 5.5
0.03
0.03
Output delay time
tdDO
SO0(P10), SO1(P13),
SB0(P11), SB1(P14)
•Measured with respect
to SI0CLK trailing edge.
•When port is open
drain: Time delay
from SI0CLK trailing
edge to the SO data
change.
•Refer to figure 5
4.5 to 5.5
typ max unit
tCYC
tCYC
1/2
3/4
tSCK
1/2
2
tCYC
1/2
tSCK
1/2
µs
1/3
tCYC
+0.05
µs
Pulse Input Conditions / Ta=-30°C to +70°C, VSS1=0V
Parameter
Symbol
Pins
Conditions
High / low level
pulse width
tPIH(1)
tPIL(1)
tPIH(2)
tPIL(2)
tPIH(3)
tPIL(3)
tPIH(4)
tPIL(4)
tPIL(5)
INT0(P70),
INT1(P71),
INT2(P72)
INT3(P73)
(Noise rejection ratio set
to 1/1.)
INT3(P73)
(Noise rejection ratio set
to 1/32.)
INT3(P73)
(Noise rejection ratio set
to 1/128.)
RES
•Interrupt acceptable
•Events to timer 0 can
be
input.
•Interrupt acceptable
•Events to timer 0 can
be
input.
•Interrupt acceptable
•Events to timer 0 can
be
input.
•Interrupt acceptable
•Events to timer 0 can
be
input.
•Reset possible
VDD [V]
min
typ
4.5 to 5.5
1
4.5 to 5.5
2
4.5 to 5.5
64
4.5 to 5.5
4.5 to 5.5
256
200
max unit
tCYC
µs
No.7373-11/17
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet LC876124A.PDF ] | |
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