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PDF XPC850EC Data sheet ( Hoja de datos )

Número de pieza XPC850EC
Descripción 1 Chip Integrated Microprocessor
Fabricantes Freescale Semiconductor 
Logotipo Freescale Semiconductor Logotipo



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Advance Information
MPC850EC/D
Rev. 0.2, 04/2002
MPC850 (Rev. A/B/C)
Communications Controller
Hardware Specifications
This document contains detailed information on power considerations, AC/DC electrical
characteristics, and AC timing specifications for revision A,B, and C of the MPC850.
This document contains the following topics:
Topic
Page
Part I, “Overview”
Part II, “Features”
Part III, “Electrical and Thermal Characteristics”
Part IV, “Thermal Characteristics”
Part V, “Power Considerations”
Part VI, “Bus Signal Timing”
Part VII, “IEEE 1149.1 Electrical Specifications”
Part VIII, “CPM Electrical Characteristics”
Part IX, “Mechanical Data and Ordering Information”
Part X, “Document Revision History”
1
3
7
8
9
10
37
39
61
67
Part I Overview
The MPC850 is a versatile, one-chip integrated microprocessor and peripheral combination
that can be used in a variety of controller applications, excelling particularly in
communications and networking products. The MPC850, which includes support for
Ethernet, is specifically designed for cost-sensitive, remote-access, and telecommunications
applications. It is provides functions similar to the MPC860, with system enhancements such
as universal serial bus (USB) support and a larger (8-Kbyte) dual-port RAM.
In addition to a high-performance embedded MPC8xx core, the MPC850 integrates system
functions, such as a versatile memory controller and a communications processor module
(CPM) that incorporates a specialized, independent RISC communications processor
(referred to as the CP). This separate processor off-loads peripheral tasks from the embedded
MPC8xx core.
The CPM of the MPC850 supports up to seven serial channels, as follows:
• One or two serial communications controllers (SCCs). The SCCs support Ethernet,
ATM (MPC850SAR), HDLC and a number of other protocols, along with a
transparent mode of operation.

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XPC850EC pdf
— Interrupt can be masked on reference match and event capture
• Interrupts
— Eight external interrupt request (IRQ) lines
— Twelve port pins with interrupt capability
— Fifteen internal interrupt sources
— Programmable priority among SCCs and USB
— Programmable highest-priority request
• Single socket PCMCIA-ATA interface
— Master (socket) interface, release 2.1 compliant
— Single PCMCIA socket
— Supports eight memory or I/O windows
• Communications processor module (CPM)
— 32-bit, Harvard architecture, scalar RISC communications processor (CP)
— Protocol-specific command sets (for example, GRACEFUL STOP TRANSMIT stops transmission
after the current frame is finished or immediately if no frame is being sent and CLOSE RXBD
closes the receive buffer descriptor)
— Supports continuous mode transmission and reception on all serial channels
— Up to 8 Kbytes of dual-port RAM
— Twenty serial DMA (SDMA) channels for the serial controllers, including eight for the four
USB endpoints
— Three parallel I/O registers with open-drain capability
• Four independent baud-rate generators (BRGs)
— Can be connected to any SCC, SMC, or USB
— Allow changes during operation
— Autobaud support option
• Two SCCs (serial communications controllers)
— Ethernet/IEEE 802.3, supporting full 10-Mbps operation
— HDLC/SDLC™ (all channels supported at 2 Mbps)
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support PPP (point-to-point protocol)
— AppleTalk®
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Totally transparent (bit streams)
— Totally transparent (frame based with optional cyclic redundancy check (CRC))
• QUICC multichannel controller (QMC) microcode features
— Up to 64 independent communication channels on a single SCC
— Arbitrary mapping of 0–31 channels to any of 0–31 TDM time slots
MOTOROLA
MPC850 (Rev. A/B/C) Hardware Specifications
5

5 Page





XPC850EC arduino
Layout Practices
Table 6. Bus Operation Timing 1
Num
Characteristic
50 MHz
Min Max
66 MHz
Min Max
80 MHz
Cap Load
FFACT (default Unit
Min Max
50 pF)
B1 CLKOUT period
20 — 30.30 — 25 —
B1a EXTCLK to CLKOUT phase
skew (EXTCLK > 15 MHz and
MF <= 2)
-0.90 0.90 -0.90 0.90 -0.90 0.90
B1b EXTCLK to CLKOUT phase
skew (EXTCLK > 10 MHz and
MF < 10)
-2.30 2.30 -2.30 2.30 -2.30 2.30
B1c CLKOUT phase jitter (EXTCLK > -0.60 0.60 -0.60 0.60 -0.60 0.60
15 MHz and MF <= 2) 2
B1d CLKOUT phase jitter 2
-2.00 2.00 -2.00 2.00 -2.00 2.00
B1e CLKOUT frequency jitter (MF < — 0.50 — 0.50 — 0.50
10) 2
B1f CLKOUT frequency jitter (10 <
MF < 500) 2
— 2.00 — 2.00 — 2.00
B1g CLKOUT frequency jitter (MF > — 3.00 — 3.00 — 3.00
500) 2
B1h Frequency jitter on EXTCLK 3
— 0.50 — 0.50 — 0.50
B2 CLKOUT pulse width low
8.00 — 12.12 — 10.00 —
B3 CLKOUT width high
8.00 — 12.12 — 10.00 —
B4 CLKOUT rise time
— 4.00 — 4.00 — 4.00 —
B5 CLKOUT fall time
— 4.00 — 4.00 — 4.00 —
B7 CLKOUT to A[6–31],
RD/WR, BURST, D[0–31],
DP[0–3] invalid
5.00 — 7.58 — 6.25 — 0.250
B7a CLKOUT to TSIZ[0–1], REG,
5.00 — 7.58 — 6.25 — 0.250
RSV, AT[0–3], BDIP, PTR invalid
B7b CLKOUT to BR, BG, FRZ,
5.00 — 7.58 — 6.25 — 0.250
VFLS[0–1], VF[0–2] IWP[0–2],
LWP[0–1], STS invalid 4
B8 CLKOUT to A[6–31],
RD/WR, BURST, D[0–31],
DP[0–3] valid
5.00 11.75 7.58 14.33 6.25 13.00 0.250
B8a CLKOUT to TSIZ[0–1], REG,
RSV, AT[0–3] BDIP, PTR valid
5.00 11.75 7.58 14.33 6.25 13.00 0.250
B8b CLKOUT to BR, BG, VFLS[0–1], 5.00 11.74 7.58 14.33 6.25 13.00 0.250
VF[0–2], IWP[0–2], FRZ,
LWP[0–1], STS valid 4
B9 CLKOUT to A[6–31] RD/WR,
5.00 11.75 7.58 14.33 6.25 13.00 0.250
BURST, D[0–31], DP[0–3],
TSIZ[0–1], REG, RSV, AT[0–3],
PTR high-Z
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
ns
ns
ns
ns
ns
%
%
%
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MOTOROLA
MPC850 (Rev. A/B/C) Hardware Specifications
11

11 Page







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