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PDF EN25F80 Data sheet ( Hoja de datos )
| Número de pieza | EN25F80 | |
| Descripción | 8 Mbit Serial Flash Memory | |
| Fabricantes | Eon | |
| Logotipo |  |
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EN25F80
EN25F80
8 Mbit Serial Flash Memory with 4Kbytes Uniform Sector
FEATURES
• Single power supply operation
- Full voltage range: 2.7-3.6 volt
• 8 Mbit Serial Flash
- 8 M-bit/1024 K-byte/4096 pages
- 256 bytes per programmable page
• High performance
- 100MHz clock rate
• Low power consumption
- 5 mA typical active current
- 1 μA typical power down current
• Uniform Sector Architecture:
- 256 sectors of 4-Kbyte
- 16 blocks of 64-Kbyte
- Any sector or block can be
erased individually
• Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
• High performance program/erase speed
- Page program time: 1.5ms typical
- Sector erase time: 150ms typical
- Block erase time 800ms typical
- Chip erase time: 10 Seconds typical
• Lockable 256 byte OTP security sector
• Minimum 100K endurance cycle
• Package Options
- 8 pins SOP 200mil body width
- 8 contact VDFN
- 8 pins PDIP
- All Pb-free packages are RoHS compliant
• Commercial and industrial temperature
Range
GENERAL DESCRIPTION
The EN25F80 is a 8M-bit (1024K-byte) Serial Flash memory, with advanced write protection
mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to
256 bytes at a time, using the Page Program instruction.
The EN25F80 is designed to allow either single Sector at a time or full chip erase operation. The
EN25F80 can be configured to protect part of the memory as the software protected mode. The device
can sustain a minimum of 100K program/erase cycles on each sector.
This Data Sheet may be revised by subsequent versions 1
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. D, Issue Date: 2007/05/16
1 page  
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Table 2. Uniform Block Sector Architecture
Block
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Sector
255
240
239
224
223
208
207
192
191
176
175
160
159
144
143
128
127
112
111
96
95
80
79
64
63
48
47
32
31
16
15
4
3
2
1
0
Address range
0FF000h
0FFFFFh
0F0000h
0EF000h
0F0FFFh
0EFFFFh
0E0000h
0DF000h
0E0FFFh
0DFFFFh
0D0000h
0CF000h
0D0FFFh
0CFFFFh
0C0000h
0BF000h
0C0FFFh
0BFFFFh
0B0000h
0AF000h
0B0FFFh
0AFFFFh
0A0000h
09F000h
0A0FFFh
09FFFFh
090000h
08F000h
090FFFh
08FFFFh
080000h
07F000h
080FFFh
07FFFFh
070000h
06F000h
070FFFh
06FFFFh
060000h
05F000h
060FFFh
05FFFFh
050000h
04F000h
050FFFh
04FFFFh
040000h
03F000h
040FFFh
03FFFFh
030000h
02F000h
030FFFh
02FFFFh
020000h
01F000h
020FFFh
01FFFFh
010000h
00F000h
010FFFh
00FFFFh
004000h
003000h
002000h
001000h
000000h
004FFFh
003FFFh
002FFFh
001FFFh
000FFFh
EN25F80
This Data Sheet may be revised by subsequent versions
5
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. D, Issue Date: 2007/05/16
5 Page 
www.DataSheet4U.com
EN25F80
Read Status Register (RDSR) (05h)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register
may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress.
When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit
before sending a new instruction to the device. It is also possible to read the Status Register continuously,
as shown in Figure 7.
Table 6. Status Register Bit Locations
Note : In OTP mode, SRP bit is served as OTP_LOCK bit.
The status and control bits of the Status Register are as follows:
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When
set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and
no Write Status Register, Program or Erase instruction is accepted.
BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the
area to be software protected against Program and Erase instructions. These bits are written with the
Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP2, BP1, BP0) bits is
set to 1, the relevant memory area (as defined in Table 3.) becomes protected against Page Program (PP)
Sector Erase (SE) and , Block Erase (BE), instructions. The Block Protect (BP2, BP1, BP0) bits can be
written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) instruction is
executed if, and only if, both Block Protect (BP2, BP1, BP0) bits are 0.
This Data Sheet may be revised by subsequent versions 11 ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. D, Issue Date: 2007/05/16
11 Page | ||
| Páginas | Total 33 Páginas | |
| PDF Descargar | [ Datasheet EN25F80.PDF ] | |
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