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PDF EN25B80 Data sheet ( Hoja de datos )
| Número de pieza | EN25B80 | |
| Descripción | 8 Mbit Serial Flash Memory | |
| Fabricantes | Eon | |
| Logotipo |  |
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EN25B80
EN25B80
8 Mbit Serial Flash Memory with Boot and Parameter Sectors
FEATURES
• Single power supply operation
- Full voltage range: 2.7-3.6 volt
• 8 M-bit Serial Flash
- 8 M-bit/1024 K-byte/4096 pages
- 256 bytes per programmable page
• High performance
- 75MHz clock rate
• Low power consumption
- 5 mA typical active current
- 1 μA typical power down current
• Flexible Sector Architecture:
- Two 4-Kbyte, one 8-Kbyte, one 16-Kbyte,one
32-Kbyte, and fifteen 64-Kbyte sectors
• Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
• High performance program/erase speed
- Byte program time: 7µs typical
- Page program time: 1.5ms typical
- Sector erase time: 300 to 800ms typical
- Chip erase time: 10 Seconds typical
• Minimum 100K endurance cycle
• Package Options
- 8 pins SOP 200mil body width
- 8 contact VDFN
- 8 pins PDIP
- All Pb-free packages are RoHS compliant
• Commercial and industrial temperature
Range
GENERAL DESCRIPTION
The EN25B80 is a 8M-bit (1024K-byte) Serial Flash memory, with advanced write protection
mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to
256 bytes at a time, using the Page Program instruction.
The EN25B80 has twenty sectors including fifteen sectors of 64KB, one sector of 32KB, one sector of
16KB, one sector of 8KB and two sectors of 4KB. This device is designed to allow either single Sector at a
time or full chip erase operation. The EN25B80 can protect boot code stored in the small sectors for either
bottom or top boot configurations. The device can sustain a minimum of 100K program/erase cycles on
each sector.
This Data Sheet may be revised by subsequent versions 1
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2006/12/25
1 page  
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EN25B80
Table 2b. Top Boot Block Sector Architecture (Special order)
Sector
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SECTOR SIZE (KByte)
4
4
8
16
32
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
Address range
FF000h – FFFFFh
FE000h – FEFFFh
FC000h – FDFFFh
F8000h – FBFFFh
F0000h – F7FFFh
E0000h – EFFFFh
D0000h – DFFFFh
C0000h – CFFFFh
B0000h – BFFFFh
A0000h – AFFFFh
90000h – 9FFFFh
80000h – 8FFFFh
70000h – 7FFFFh
60000h – 6FFFFh
50000h – 5FFFFh
40000h – 4FFFFh
30000h – 3FFFFh
20000h – 2FFFFh
10000h – 1FFFFh
00000h – 0FFFFh
This Data Sheet may be revised by subsequent versions
5
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2006/12/25
5 Page 
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EN25B80
Write Enable (WREN) (06h)
The Write Enable (WREN) instruction (Figure 5) sets the Write Enable Latch (WEL) bit. The Write Enable
Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and
Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending the instruction
code, and then driving Chip Select (CS#) High.
Write Disable (WRDI) (04h)
The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status Register to
a 0. The Write Disable instruction is entered by driving Chip Select (CS#) low, shifting the instruction code
“04h” into the DI pin and then driving Chip Select (CS#) high. Note that the WEL bit is automatically reset
after Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, and Bulk
Erase instructions.
This Data Sheet may be revised by subsequent versions 11 ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2006/12/25
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EN25B80.PDF ] | |
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