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PDF EN25B20 Data sheet ( Hoja de datos )
| Número de pieza | EN25B20 | |
| Descripción | 2 Mbit Serial Flash Memory | |
| Fabricantes | Eon | |
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EN25B20
EN25B20
2 Mbit Serial Flash Memory with Boot and Parameter Sectors
FEATURES
• Single power supply operation
- Full voltage range: 2.7-3.6 volt
• 2 M-bit Serial Flash
- 2 M-bit/256 K-byte/1024 pages
- 256 bytes per programmable page
• High performance
- 75MHz clock rate
• Low power consumption
- 5 mA typical active current
- 1 μA typical power down current
• Flexible Sector Architecture:
- Two 4-Kbyte, one 8-Kbyte, one 16-Kbyte,one
32-Kbyte, and three 64-Kbyte sectors
• Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
• High performance program/erase speed
- Byte program time: 7µs typical
- Page program time: 1.5ms typical
- Sector erase time: 300 to 800ms typical
- Chip erase time: 3 Seconds typical
• Minimum 100K endurance cycle
• Package Options
- 8 pins SOP 150mil body width
- 8 contact VDFN
- All Pb-free packages are RoHS compliant
• Commercial and industrial temperature Range
GENERAL DESCRIPTION
The EN25B20 is a 2M-bit (256K-byte) Serial Flash memory, with advanced write protection
mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to
256 bytes at a time, using the Page Program instruction.
The EN25B20 has eight sectors including three sectors of 64KB, one sector of 32KB, one sector of
16KB, one sector of 8KB and two sectors of 4KB. This device is designed to allow either single
Sector at a time or full chip erase operation. The EN25B20 can protect boot code stored in the small
sectors for either bottom or top boot configurations. The device can sustain a minimum of 100K
program/erase cycles on each sector.
This Data Sheet may be revised by subsequent versions 1
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2006/12/26
1 page  
www.DataSheet4U.com
EN25B20
OPERATING FEATURES
SPI Modes
The EN25B20 is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK),
Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation Modes 0
(0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3, as shown in Figure
3, concerns the normal state of the SCK signal when the SPI bus master is in standby and data is not
being transferred to the Serial Flash. For Mode 0 the SCK signal is normally low. For Mode 3 the SCK
signal is normally high. In either case data input on the DI pin is sampled on the rising edge of the SCK.
Data output on the DO pin is clocked out on the falling edge of SCK.
Figure 3. SPI Modes
Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a
Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal
Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at
a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of
memory.
Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the
bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time,
using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE)
instruction. This starts an internal Erase cycle (of duration tSE or tBE). The Erase instruction must be
preceded by a Write Enable (WREN) instruction.
Polling During a Write, Program or Erase Cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE or BE)
can be achieved by not waiting for the worst case delay (tW, tPP, tSE, or tBE). The Write In Progress
(WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it
to establish when the previous Write cycle, Program cycle or Erase cycle is complete.
Active Power, Stand-by Power and Deep Power-Down Modes
When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip Select
(CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles
have completed (Program, Erase, Write Status Register). The device then goes in to the Stand-by Power
mode. The device consumption drops to ICC1.
The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down Mode
(DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in this
mode until another specific instruction (the Release from Deep Power-down Mode and Read Device ID
(RDI) instruction) is executed.
All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as
an extra software protection mechanism, when the device is not in active use, to protect the device from
inadvertent Write, Program or Erase instructions.
This Data Sheet may be revised by subsequent versions
5
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2006/12/26
5 Page 
www.DataSheet4U.com
Table 6. Status Register Bit Locations
EN25B20
The status and control bits of the Status Register are as follows:
BUSY bit. The BUSY bit indicates whether the memory is busy with a Write Status Register, Program or
Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When
set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and
no Write Status Register, Program or Erase instruction is accepted.
BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the
area to be software protected against Program and Erase instructions. These bits are written with the
Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP2, BP1, BP0) bits is
set to 1, the relevant memory area (as defined in Table 3.) becomes protected against Page Program (PP)
and Sector Erase (SE) instructions. The Block Protect (BP2, BP1, BP0) bits can be written provided that
the Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if,
both Block Protect (BP2, BP1, BP0) bits are 0.
Reserved bit. Status register bit locations 5 and 6 are reserved for future use. Current devices will read 0
for these bit locations. It is recommended to mask out the reserved bit when testing the Status Register.
Doing this will ensure compatibility with future devices.
SRP bit. The Status Register Protect (SRP) bit is operated in conjunction with the Write Protect (WP#)
signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal allow the device to be
put in the Hardware Protected mode (when the Status Register Protect (SRP) bit is set to 1, and Write
Protect (WP#) is driven Low). In this mode, the non-volatile bits of the Status Register (SRP, BP2, BP1,
BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for
execution.
This Data Sheet may be revised by subsequent versions 11 ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2006/12/26
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EN25B20.PDF ] | |
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