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PDF S29GL064A Data sheet ( Hoja de datos )

Número de pieza S29GL064A
Descripción 64 Megabit 3.0-Volt only Page Mode Flash Memory
Fabricantes SPANSION 
Logotipo SPANSION Logotipo



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ADVANCE
INFORMATION
S29GLxxxA MirrorBit™ Flash Family
S29GL064A, S29GL032A
64 Megabit, 32 Megabit 3.0, Volt-only Page Mode Flash
Memory Featuring 200 nm MirrorBit Process Technology
Data Sheet
Notice to Readers: The Advance Information status indicates that this
document contains information on one or more products under development
at Spansion LLC. The information is intended to help you evaluate this product.
Do not design in this product without contacting the factory. Spansion LLC
reserves the right to change or discontinue work on this proposed product
without notice.
Publication Number S29GLxxxA_00 Revision A Amendment 2 Issue Date January 28, 2005

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S29GL064A pdf
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Advance Information
General Description
The S29GLxxxA family of devices are 3.0 V single power Flash memory manufac-
tured using 200 nm MirrorBit technology. The S29GL064A is a 64 Mb, organized
as 4,194,304 words or 8,388,608 bytes. The S29GL032A is a 32 Mb, organized
as 2,097,152 words or 4,194,304 bytes. Depending on the model number, the
devices have an 8-bit wide data bus only, 16-bit wide data bus only, or a 16-bit
wide data bus that can also function as an 8-bit wide data bus by using the BYTE#
input. The devices can be programmed either in the host system or in standard
EPROM programmers.
Access times as fast as 90 ns are available. Note that each access time has a spe-
cific operating voltage range (VCC) as specified in the Product Selector Guide and
the Ordering Information sections. Package offerings include 48-pin TSOP, 56-pin
TSOP, 48-ball fine-pitch BGA and 64-ball Fortified BGA, depending on model num-
ber. Each device has separate chip enable (CE#), write enable (WE#) and output
enable (OE#) controls.
Each device requires only a single 3.0 volt power supply for both read and
write functions. In addition to a VCC input, a high-voltage accelerated program
(ACC) feature provides shorter programming times through increased current on
the WP#/ACC input. This feature is intended to facilitate factory throughput dur-
ing system production, but may also be used in the field if desired.
The device is entirely command set compatible with the JEDEC single-power-
supply Flash standard. Commands are written to the device using standard mi-
croprocessor write timing. Write cycles also internally latch addresses and data
needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through command sequences.
Once a program or erase operation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy#
(RY/BY#) output to determine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces command sequence overhead
by requiring only two write cycles to program data instead of four.
Hardware data protection measures include a low VCC detector that automat-
ically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase operations in any combina-
tion of sectors of memory. This can be achieved in-system or via programming
equipment.
The Erase Suspend/Erase Resume feature allows the host system to pause an
erase operation in a given sector to read or program any other sector and then
complete the erase operation. The Program Suspend/Program Resume fea-
ture enables the host system to pause a program operation in a given sector to
read any other sector and then complete the program operation.
The hardware RESET# pin terminates any operation in progress and resets the
device, after which it is then ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would thus also reset the device,
enabling the host system to read boot-up firmware from the Flash memory
device.
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
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S29GL064A arduino
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Advance Information
64-ball Fortified BGA
Top View, Balls Facing Down
A8 B8 C8
NC NC NC
A7 B7 C7
A13 A12 A14
A6 B6 C6
A9 A8 A10
A5 B5 C5
WE# RESET# A213
A4 B4 C4
RY/BY# WP#/ACC A18
A3 B3 C3
A7 A17 A6
A2 B2 C2
A3 A4 A2
A1 B1 C1
NC NC NC
D8
VIO1
D7
A15
D6
A11
D5
A19
D4
A20
D3
A5
D2
A1
D1
NC
E8 F8 G8 H8
VSS NC
NC NC
E7 F7 G7 H7
A16 BYTE#2 DQ15/A-1 VSS
E6
DQ7
F6
DQ14
G6
DQ13
H6
DQ6
E5
DQ5
F5
DQ12
G5
VCC
H5
DQ4
E4
DQ2
F4
DQ10
G4
DQ11
H4
DQ3
E3
DQ0
F3
DQ8
G3
DQ9
H3
DQ1
E2 F2 G2 H2
A0 CE# OE# VSS
E1 F1 G1
NC VIO4 NC
H1
NC
Notes:
1. Ball D8 and Ball F1 are NC on S29GL064A (models R3, R4).
2. Ball F7 is NC on S29GL064A (model R5).
3. Ball C5 is NC on S29GL032A.
Special Package Handling Instructions
Special handling is required for Flash Memory products in moulded packages
(TSOP and BGA). The package and/or data integrity may be compromised if the
package body is exposed to temperatures above 150°C for prolonged periods of
time.
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
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