PDF ICS951413 Data sheet ( Hoja de datos )

Número de pieza	ICS951413
Descripción	Programmable System Clock Chip
Fabricantes	ICS
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ICS951413 Programmable System Clock Chip for ATI RS400 P4TM-based Systems Recommended Application: ATI RS400 systems using Intel P4TM processors Output Features: • 6 - Pairs of SRC/PCI Express* clocks • 2 - Pairs of programmable SRC/PCI Express (ATIG) clocks • 3 - Pairs of Intel P4 clocks • 3 - 14.318 MHz REF clocks • 1 - 48MHz USB clock • 1 - 33 MHz PCI clock seed Features/Benefits: • 2 - Programmable Clock Request pins for SRC clocks • Supports CK410 or CK409 frequency table mapping • Spread Spectrum for EMI reduction • Outputs may be disabled via SMBus • External crystal load capacitors for maximum frequency accuracy Key Specifications: • CPU outputs cycle-cycle jitter < 85ps • SRC output cycle-cycle jitter <125ps • PCI outputs cycle-cycle jitter < 250ps • +/- 300ppm frequency accuracy on CPU & SRC clocks Functionality - (CK410# = 0) FS_C1 FS_B1 FS_A1 CPU MHz SRC MHz PCI MHz 0 0 266.66 100.00 33.33 0 1 133.33 100.00 33.33 1 0 200.00 100.00 33.33 1 166.66 100.00 33.33 0 0 333.33 100.00 33.33 1 1 100.00 100.00 33.33 1 0 400.00 100.00 33.33 1 RESERVED REF USB MHz MHz 14.318 48.000 14.318 48.000 14.318 48.000 14.318 48.000 14.318 48.000 14.318 48.000 14.318 48.000 14.318 48.000 Functionality - (CK410# = 1) FS_C1 Byte6 FS_B1 FS_A1 CPU MHz bit5 SRC MHz PCI MHz REF MHz USB MHz 0 0 100.00 100.00 33.33 14.318 48.000 0 1 0 200.00 100.00 33.33 14.318 48.000 0 1 133.33 100.00 33.33 14.318 48.000 1 1 166.67 100.00 33.33 14.318 48.000 0 0 200.00 100.00 33.33 14.318 48.000 1 1 0 400.00 100.00 33.33 14.318 48.000 0 1 266.67 100.00 33.33 14.318 48.000 1 1 333.33 100.00 33.33 14.318 48.000 1. FS_C, FS_B and FS_A are low-threshold inputs. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Pin Configuration X1 1 X2 2 VDD48 3 USB_48MHz 4 GND 5 VTT_PWRGD#/PD 6 SCLK 7 SDATA 8 FS_C 9 CLKREQA# 10 CLKREQB# 11 SRCCLKT7 12 SRCCLKC7 13 VDDSRC 14 GNDSRC 15 SRCCLKT6 16 SRCCLKC6 17 SRCCLKT5 18 SRCCLKC5 19 GNDSRC 20 VDDSRC 21 SRCCLKT4 22 SRCCLKC4 23 SRCCLKT3 24 SRCCLKC3 25 GNDSRC 26 ATIGCLKT1 27 ATIGCLKC1 28 56 VDDREF 55 GND 54 FS_A/REF0 53 FS_B/REF1 52 TEST_SEL/REF2 51 VDDPCI 50 *CK410#/PCICLK0 49 GNDPCI 48 CPU_STOP# 47 CPUCLKT0 46 CPUCLKC0 45 VDDCPU 44 GNDCPU 43 CPUCLKT1 42 CPUCLKC1 41 CPUCLKT2_ITP 40 CPUCLKC2_ITP 39 VDDA 38 GNDA 37 IREF 36 GNDSRC 35 VDDSRC 34 SRCCLKT0 33 SRCCLKC0 32 VDDATI 31 GNDATI 30 ATIGCLKT0 29 ATIGCLKC0 Note: Pins preceeded by '*' have a 120 Kohm Internal Pull Down resistor Pins preceeded by '' have a 120 Kohm Internal Pull Up resistor 56-pin SSOP & TSSOP 0929C—03/07/05 Other names and brands may be claimed as the property of others. 1 page www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS951413 General SMBus serial interface information for the ICS951413 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 (H) • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ICS clock will acknowledge • Controller (host) sends the data byte count = X • ICS clock will acknowledge • Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit How to Read: • Controller (host) will send start bit. • Controller (host) sends the write address D2 (H) • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ICS clock will acknowledge • Controller (host) will send a separate start bit. • Controller (host) sends the read address D3 (H) • ICS clock will acknowledge • ICS clock will send the data byte count = X • ICS clock sends Byte N + X -1 • ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). • Controller (host) will need to acknowledge each byte • Controllor (host) will send a not acknowledge bit • Controller (host) will send a stop bit Index Block Write Operation Controller (Host) ICS (Slave/Receiver) T starT bit Slave Address D2(H) WR WRite ACK Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK Byte N + X - 1 P stoP bit ACK Index Block Read Operation Controller (Host) ICS (Slave/Receiver) T starT bit Slave Address D2(H) WR WRite ACK Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK ACK ACK Data Byte Count = X Beginning Byte N N Not acknowledge P stoP bit Byte N + X - 1 0929C—03/07/05 5 5 Page www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS951413 SMBus Table: Device ID Register Byte 6 Pin # Name Bit 7 - DevID 7 Bit 6 - DevID 6 Bit 5 - DevID 5 Bit 4 - DevID 4 Bit 3 - DevID 3 Bit 2 - DevID 2 Bit 1 - DevID 1 Bit 0 - DevID 0 Control Function Device ID MSB Device ID 6 Device ID 5 Device ID4 Device ID3 Device ID2 Device ID1 Device ID LSB Type R R R R R R R R 0 - - - - - - - - 1 PWD -0 -0 -0 -1 -0 -0 -1 -1 SMBus Table: Vendor ID Register Byte 7 Pin # Name Bit 7 - RID3 Bit 6 - RID2 Bit 5 - RID1 Bit 4 - RID0 Bit 3 - VID3 Bit 2 - VID2 Bit 1 - VID1 Bit 0 - VID0 Control Function Revision ID Starts at 0 hex for A revsion. VENDOR ID (0001 = ICS) Type R R R R R R R R 0 - - - - - - - - 1 PWD -X -X -X -X -0 -0 -0 -1 SMBus Table: Byte Count Register Byte 8 Pin # Name Bit 7 - BC7 Bit 6 - BC6 Bit 5 - BC5 Bit 4 - BC4 Bit 3 - BC3 Bit 2 - BC2 Bit 1 - BC1 Bit 0 - BC0 Control Function Byte Count Programming b(7:0) Type 0 1 RW RW RW Writing to this register will RW configure how many RW bytes will be read back, RW default is 9 bytes. RW RW PWD 0 0 0 0 1 0 0 1 SMBus Table: WD TimeR Control Register Byte 9 Pin # Name Control Function Bit 7 - WDH_EN Watchdog Hard Alarm Enable Bit 6 - WDS_EN Watchdog Soft Alarm Enable Bit 5 - WD Hard Status WD Hard Alarm Status Bit 4 - WD Soft Status WD Soft Alarm Status Bit 3 - WDTCtrl Watch Dog Time base Control Bit 2 - WD2 WD Timer Bit 2 Bit 1 - WD1 WD Timer Bit 1 Bit 0 - WD0 WD Timer Bit 0 Type 0 RW Disable 1 Enable RW Disable Enable R Normal Alarm R Normal Alarm RW 290ms Base 1160ms Base RW These bits represent X290ms (or 1.16S) the RW watchdog timer waits before it goes to alarm mode. Default is 7 X RW 290ms = 2s. 0929C—03/07/05 PWD 0 0 X X 0 1 1 1 11 11 Page

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