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PDF ICS951402 Data sheet ( Hoja de datos )

Número de pieza ICS951402
Descripción Programmable Timing Control Hub
Fabricantes ICS 
Logotipo ICS Logotipo



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Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
Programmable Timing Control Hub™ for P4™ processor
Recommended Application:
ATI chipset, P4 system, Banias system
Output Features:
• 2 - Pairs of differential CPUCLKs (differential current mode)
• 1 - SDRAM @ 3.3V
• 8 - PCI @3.3V (selectable 33/66 MHz) (2 free-running)
• 2 - AGP @ 3.3V
• 2- 48MHz, @3.3V fixed.
• 1- 24/48MHz, @3.3V selectable by I2C
(Default is 24MHz)
• 3- REF @3.3V, 14.318MHz.
Features/Benefits:
• Support for Intel Banias power management features
• Programmable output frequency, divider ratios, output rise/
falltime, output skew.
• Programmable spread percentage for EMI control.
• Watchdog timer technology to reset system
if system malfunctions.
• Programmable watch dog safe frequency.
• Support I2C Index read/write and block read/write
operations.
• Supports spread spectrum for EMI reduction; default is
spread spectrum ON.
Pin Configuration
VDDREF 1
FS0/REF0 2
FS1/REF1 3
FS2/REF2 4
GNDREF 5
X1 6
X2 7
GND 8
VDD 9
*VttPWR_GD/PD# 10
PCI66/33#_SEL 11
PCI_STOP#* 12
VDDPCI 13
FS3/PCICLK_F0 14
FS4/PCICLK_F1 15
PCICLK0 16
PCICLK1 17
GNDPCI 18
VDDPCI 19
PCICLK2 20
PCICLK3 21
PCICLK4 22
PCICLK5 23
GNDPCI 24
48 VDDSDR
47 SDRAM_OUT
46 GNDSDR
45 CPU_STOP#*
44 CPUCLKT1
43 CPUCLKC1
42 VDDCPU
41 GNDCPU
40 CPUCLKT0
39 CPUCLKC0
38 IREF
37 GND
36 AVDD
35 SCLK
34 SDATA
33 GNDAGP
32 AGPCLK0
31 AGPCLK1
30 VDDAGP
29 AVDD48
28 48MHz_0
27 48MHz_1
26 24_48MHz/SEL24_48#MHz**
25 GND48
48-Pin TSSOP & SSOP
* These inputs have a 120K pull up to VDD.
** These inputs have a 120K pull down to GND.
Block Diagram
PLL2
X1 XTAL
X2 OSC
PLL1
Spread
Spectrum
/2
CPU
DIVDER
Stop
Skew Requirements
48MHz (0:1)
24_48MHz
REF (2:0)
3
2 CPUCLKT (1:0)
2 CPUCLKC (1:0)
PCI-PCI
AGP-AGP
CPU-AGP
CPU-PCI
AGP-PCI
AGP leading
CPU-SDRAM
<±350ps
<±350ps
<±500ps
<±500ps
<±1ns
<±1ns
SDATA
SCLK
FS (4:0)
PD#
PCI_STOP#
CPU_STOP#
PD#/Vtt_PWRGD
PCI66/33#SEL
24_48SEL#
Control
Logic
Config.
Reg.
SDRAM
PCI
DIVDER
Stop
AGP
DIVDER
SDRAM_OUT
1
6 PCICLK (5:0)
PCICLK_F (1:0)
2
AGP (1:0)
2
I REF
Power Groups
VDDCPU = CPU
VDDPCI = PCICLK_F, PCICLK
VDDSD = SDRAM
AVDD48 = 48MHz, 24MHz, fixed PLL
AVDD = Analog Core PLL
VDDAGP= AGP
VDDREF = Xtal, REF
0660—05/05/05
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.

1 page




ICS951402 pdf
www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
Serial Configuration Command Bitmap
CPU MHz
FS4 FS3 FS2 FS1 FS0
0 0 0 0 0 100.00
0 0 0 0 1 133.34
0 0 0 1 0 200.01
0 0 0 1 1 166.65
0 0 1 0 0 100.00
0 0 1 0 1 133.34
0 0 1 1 0 133.16
0 0 1 1 1 166.45
0 1 0 0 0 105.00
0 1 0 0 1 140.00
0 1 0 1 0 66.67
0 1 0 1 1 175.00
0 1 1 0 0 109.99
0 1 1 0 1 146.65
0 1 1 1 0 210.00
0 1 1 1 1 183.27
1 0 0 0 0 99.51
1 0 0 0 1 132.68
1 0 0 1 0 199.02
1 0 0 1 1 165.85
1 0 1 0 0 99.51
1 0 1 0 1 132.68
1 0 1 1 0 132.59
1 0 1 1 1 165.73
1 1 0 0 0 99.39
1 1 0 0 1 132.51
1 1 0 1 0 198.77
1 1 0 1 1 165.64
1 1 1 0 0 99.39
1 1 1 0 1 132.51
1 1 1 1 0 132.36
1 1 1 1 1 165.45
SDRAM
MHz
100.00
133.34
200.01
166.65
133.34
100.00
166.45
133.16
105.00
140.00
66.67
175.00
109.99
146.65
210.00
183.27
99.51
132.68
199.02
165.85
132.68
99.51
165.73
132.59
99.39
132.51
198.77
165.64
132.51
99.39
165.45
132.36
3V66 MHz PCI MHz REF MHz USB/DOT With Spread Enabled…
MHz
66.67
66.67
66.67
66.66
66.67
66.67
66.58
66.58
70.00
70.00
66.67
70.00
73.33
73.33
70.00
73.31
66.34
66.34
66.34
66.34
66.34
66.34
66.29
66.29
66.26
66.26
66.26
66.25
66.26
66.26
66.18
66.18
33.33
33.33
33.33
33.33
33.33
33.33
33.29
33.29
35.00
35.00
33.33
35.00
36.66
36.66
35.00
36.65
33.17
33.17
33.17
33.17
33.17
33.17
33.15
33.15
33.13
33.13
33.13
33.13
33.13
33.13
33.09
33.09
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
SpreaD OFF
OR
Center spread +/-0.3%
Down Spread -0.6%
Down Spread -0.8%
0660—05/05/05
5

5 Page





ICS951402 arduino
www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
I2C Table: Output Divider Control Register
Byte 15 Pin #
Name
Control
Function
Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
SD Div3
SD Div2
SD Div1
SD Div0
CPU Div3
CPU Div2
CPU Div1
CPU Div0
SDRAM divider ratio
can be configured
via these 4 bits
individually.
CPU divider ratio can
be configured via
these 4 bits
individually.
RW
RW
RW
RW
RW
RW
RW
RW
01
See Table 2: Divider
Ratio Combination
Table
See Table 2: Divider
Ratio Combination
Table
PWD
X
X
X
X
X
X
X
X
Table 2: CPU, SDRAM, AGP and PCI66 Divider Ratio Combination Table
Divider (3:2)
Bit 00 01 10 11 MSB
124 8
00
0000
2
0100
4
1000
8
1100
16
01 0001 3 0101 6 1001 12 1101 24
10 0010 5 0110 10 1010 20 1110 40
11 0011 7 0111 14 1011 28 1111 56
LSB Address Div Address Div Address Div Address Div
Table 3: PCI33 Divider Ratio Combination Table
Divider (3:2)
Bit 00 01 10 11 MSB
124 8
00 0000 4 0100 8 1000 16 1100 32
01 0001 3 0101 6 1001 12 1101 24
10 0010 5 0110 10 1010 20 1110 40
11 0011 7 0111 14 1011 28 1111 56
LSB Address Div Address Div Address Div Address Div
0660—05/05/05
11

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