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PDF 87C196KC Data sheet ( Hoja de datos )

Número de pieza 87C196KC
Descripción Commercial / Express CHMOS Microcontroller
Fabricantes Intel 
Logotipo Intel Logotipo



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8XC196KC/8XC196KC20
COMMERCIAL/EXPRESS CHMOS
MICROCONTROLLER
87C196KC-16 Kbytes of On-Chip OTPROM
83C196KC-16 Kbytes ROM
80C196KC-ROMless
Y 16 and 20 MHz Available
Y 488 Byte Register RAM
Y Register-to-Register Architecture
Y 28 Interrupt Sources/16 Vectors
Y Peripheral Transaction Server
Y 1.4 ms 16 x 16 Multiply (20 MHz)
Y 2.4 ms 32/16 Divide (20 MHz)
Y Powerdown and Idle Modes
Y Five 8-Bit I/O Ports
Y 16-Bit Watchdog Timer
Y Extended Temperature Available
Y Dynamically Configurable 8-Bit or
16-Bit Buswidth
Y Full Duplex Serial Port
Y High Speed I/O Subsystem
Y 16-Bit Timer
Y 16-Bit Up/Down Counter with Capture
Y 3 Pulse-Width-Modulated Outputs
Y Four 16-Bit Software Timers
Y 8- or 10-Bit A/D Converter with
Sample/Hold
Y HOLD/HLDA Bus Protocol
Y OTPROM One-Time Programmable
Version
The 80C196KC 16-bit microcontroller is a high performance member of the MCS 96 microcontroller family.
The 80C196KC is an enhanced 80C196KB device with 488 bytes RAM, 16 and 20 MHz operation and an
optional 16 Kbytes of ROM/OTPR OM. Intel's CHMOS III process provides a high performance processor
along with low power consumption.
The 87C196KC is an 80C196KC with 16 Kbytes on-chip OTPROM. The 83C196KC is an 80C196KC with 16
Kbytes factory programmed ROM. In this document, the 80C196KC will refer to all products unless otherwise
stated.
Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an A/D conversion. Events can be based on the timer or up/down counter.
With the commercial (standard) temperature option, operational characteristics are guaranteed over the tem-
perature range of 0 C to a70 C. With the extended (Express) temperature range option, operational charac-
teristics are guaranteed over the temperature range of b40 C to a85 C. Unless otherwise noted, the specifi-
cations are the same for both options.
See the Packaging information for extended temperature designators.
Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
COPYRIGHT © INTELCORPORATION,2004
July 2004
Order Number:270942-006

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87C196KC pdf
8XC196KC/8XC196KC20
Figure 5. 8XC196KC 80-Pin QFP Package
270942 – 40
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87C196KC arduino
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8XC196KC/8XC196KC20
ICC Max e 4.13 c Frequency a 9 mA
ICC Typ e 3.50 c Frequency a 9 mA
IIDLE Max e 1.25 c Frequency a 5 mA
IIDLE Typ e 0.88 c Frequency a 3 mA
NOTE:
Frequencies below 8 MHz are shown for reference only; no testing is performed.
Figure 7. ICC and IIDLE vs Frequency
270942 ±17
AC CHARACTERISTICS
For use over specified operating conditions.
Test Conditions: Capacitive load on all pins e 100 pF, Rise and fall times e 10 ns, FOSC e 16 MHz
The system must meet these specifications to work with the 80C196KC:
Symbol
Description
Min Max
TAVYV
TYLYH
TCLYX
TLLYX
TAVGV
TCLGX
TAVDV
TRLDV
TCLDV
TRHDZ
TRXDX
Address Valid to READY Setup
Non READY Time
READY Hold after CLKOUT Low
READY Hold after ALE Low
Address Valid to Buswidth Setup
Buswidth Hold after CLKOUT Low
Address Valid to Input Data Valid
RD Active to Input Data Valid
CLKOUT Low to Input Data Valid
End of RD to Input Data Float
Data Hold after RD Inactive
2 TOSC b 68
No upper limit
0
TOSC b 15
0
TOSC b 30
2 TOSC b 40
2 TOSC b 68
3 TOSC b 55
TOSC b 22
TOSC b 45
TOSC
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
(Note 1)
(Note 1)
(Note 2)
(Note 2)
NOTES:
1. If max is exceeded, additional wait states will occur.
2. If wait states are used, add 2 TOSC N, where N e number of wait states.
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