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PDF COM90C66 Data sheet ( Hoja de datos )

Número de pieza COM90C66
Descripción ARCNET Controller/Transceiver
Fabricantes SMSC Corporation 
Logotipo SMSC Corporation Logotipo



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COM90C66
Data Sheet with Erratas for
Rev. B and Rev. D devices
ARCNET® Controller/Transceiver with
AT® Interface and On-Chip RAM
FEATURES
ARCNET LAN Controller/Transceiver/
Compatible with the SMSC HYC9058/68/ 88
Support Logic/Dual-Port RAM
(COAX and Twisted Pair Drivers)
Integrates SMSC COM90C65 with 16-Bit
Token Passing Protocol with Self
Data Bus, Dual-Port RAM, and Enhanced
Reconfiguration Detection
Diagnostics Circuitry
Variable Data Length Packets
Includes IBM® PC/AT® Bus Interface
16 Bits CRC Check/Generation
Circuitry
Includes Address Decoding Circuitry for On-
Supports 8- and 16-Bit Data Buses
Chip RAM, PROM and I/O
Full 2K x 8 On-Chip Dual-Port Buffer RAM
Supports up to 255 Nodes
Zero Wait State Arbitration for Most AT
Contains Software Accessible Node ID
Buses
Register
SMSC COM90C26 Software Compatible
Compatible with Various Topologies (Star,
Command Chaining Enhances Performance
Tree, Bus, ...)
Supports Memory Mapped and Sequential
On-Board Crystal Oscillator and Reset
I/O Mapped Access to the Internal RAM
Circuitry
Buffer
Low Power CMOS, Single +5V Supply
GENERAL DESCRIPTION
The SMSC COM90C66 is a special purpose device. Maximum integration has been achieved
communications controller for interconnecting by including the 2K x 8 RAM buffer on the chip,
processors and intelligent peripherals using the providing the immediate benefits of a lower
ARCNET Local Area Network. The COM90C66 device pin count and less board components.
is unique in that it integrates the core ARCNET The performance is enhanced in four ways: a
logic found in Standard Microsystems' original 16-bit data bus for operation with the IBM PC/AT;
COM90C26 and COM90C32 with an on-chip 2K a zero wait state arbitration mechanism, due
x 8 RAM, as well as the 16-bit data bus interface partly to the integration of the RAM buffer on-
for the IBM PC/AT. Because of the inclusion of chip; the ability of the device to do consecutive
the RAM buffer in the COM90C66, a complete transmissions and receptions via the Command
ARCNET node can be implemented with only Chaining operation; and improved diagnostics,
one or two additional ICs (8- or 16-bit allowing the user to control the system more
applications, respectively) and a media driver efficiently. For most AT compatibles, the device
circuit. The ARCNET core remains functionally handles zero wait state transfers.
untouched, eliminating validation and
compatibility concerns. The enhancements exist
in the integration and the performance of the
ARCNET is a registered trademark of Datapoint Corporation
IBM, AT, PC/AT and Micro Channel are registered trademarks of
International Business Machines Corporation
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DESCRIPTION OF PIN FUNCTIONS
PLCC
PIN NO.
NAME
SYMBOL
DESCRIPTION
66 nMemory Read nMEMR
Input. This active low signal is issued by the host
microprocessor to indicate a Memory Read operation. A
low level on this pin when the COM90C66 is accessed
enables data from the internal RAM of the COM90C66 or
the PROM onto the data bus to be read by the host.
67 nMemory
Write
nMEMW
Input. This active low signal is issued by the host
microprocessor to indicate a Memory Write operation. A
low pulse on this pin when the COM90C66 is accessed
enables data from the data bus into the internal RAM of
the COM90C66.
52 Reset In
RESETIN
Input. This active high signal is the power on reset signal
from the host. It is used to activate the internal reset
circuitry within the COM90C66.
53 nROM Enable nENROM Input. This active low signal enables the decoding of the
external PROM. This signal also affects the timing of
IOCHRDY and the number of address lines used to
decode nMEMCS16. This signal is connected to a weak
internal pull-up resistor.
54 nROM Select nPROM
Output. This active low signal is issued by the
COM90C66 to enable the external 8-bit wide PROM or
the external register of the COM90C66.
30 Interrupt
Request
INTR
Output. This active high signal is generated by the
COM90C66 when an enabled interrupt condition occurs.
INTR returns to its inactive state when the interrupt
status condition or the corresponding interrupt mask bit
is reset.
72 nZero Wait
State
n0WS
Output. This active low signal is used to force zero wait
state access cycles on the IBM PC Bus. This is an open-
drain signal. An external pull-up resistor is typically
provided by the system.
70 nMemory
16-Bit Chip
Select
nMEMCS16
Output. This active low signal is used to indicate that the
present data transfer is a 16-bit memory cycle. The
COM90C66 can be configured to use A19-A17 or A19-
A11 to generate nMEMCS16. This is an open-drain
signal. An external pull-up resistor is typically provided
by the system.
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COM90C66 arduino
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transmitted every 4.4 µS and the time to transmit
a message can be precisely determined. The line
idles in a spacing (logic "0") condition. A logic "0"
is defined as no line activity and a logic "1" is
defined as a negative pulse of 200 nS duration.
A transmission starts with an ALERT BURST
consisting of six unit intervals of mark (logic "1").
Eight-bit data characters are then sent with each
character preceded by two unit intervals of mark
and one unit interval of space. Five types of
transmission can be performed as described
below:
Invitations To Transmit
An Invitation To Transmit is used to pass the
token from one node to another and is sent by
the following sequence:
An ALERT BURST
An EOT (End Of Transmission--ASCII code
04 HEX)
Two (repeated) DID (Destination
IDentification) characters
ALERT
BURST
EOT
DID
DID
Free Buffer Enquiries
A Free Buffer Enquiry is used to ask another
node if it is able to accept a packet of data and
is sent by the following sequence:
An ALERT BURST
An ENQ (ENQuiry--ASCII code 85 HEX)
Two (repeated) DID (Destination
IDentification) characters
ALERT
BURST
ENQ
DID
DID
Data Packets
A Data Packet consists of the actual data being
sent to another node and is sent by the following
sequence:
An ALERT BURST
An SOH (Start Of Header--ASCII code 01
HEX)
An SID (Source IDentification) character
Two (repeated) DID (Destination
IDentification) characters
A single COUNT character which is the 2's
complement of the number of data bytes to
follow if a short packet is being sent or 00
HEX followed by a COUNT character which
is the 2's complement of the number of data
bytes to follow if a long packet is being sent
N data bytes where COUNT = 256-N (or
512-N for a long packet)
Two CRC (Cyclic Redundancy Check)
characters. The CRC polynomial used is X16
+ X15 + X2 + 1.
ALERT
BURST
SOH SID DID DID
COUNT
data
data CRC CRC
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