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PDF M11L416256SA Data sheet ( Hoja de datos )

Número de pieza M11L416256SA
Descripción 256 K x 16 DRAM EDO PAGE MODE
Fabricantes Elite Semiconductor 
Logotipo Elite Semiconductor Logotipo



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EliteMT
DRAM
M11L416256SA
256 K x 16 DRAM
EDO PAGE MODE
FEATURES
X16 organization
EDO (Extended Data-Output) access mode
2 CAS Byte/Word Read/Write operation
Single 3.3V ( ± 10%) power supply
LVTTL-compatible inputs and outputs
512-cycle refresh in 8ms
Refresh modes : RAS only, CAS BEFORE RAS (CBR)
and HIDDEN capabilities
Self-refresh capability
JEDEC standard pinout
Key AC Parameter
tRAC
tCAC
tRC
tPC
-35 35 10 65 14
ORDERING INFORMATION - PACKAGE
40-pin 400mil SOJ
44 / 40-pin 400mil TSOP (Type II)
PRODUCT NO.
PACKING
TYPE
COMMENTS
M11L416256SA-
35 TG
SOJ/TSOPII
Pb-free
M11L416256SA-
35 JP
GENERAL DESCRIPTION
The M11L416256 series is a randomly accessed solid state memory, organized as 262,144 x 16 bits device. It offers
Extended Data-Output , 3.3V( ± 10%) single power supply. Access time (-35) , self-refresh and package type (SOJ, TSOP II)
are optional features of this family. All these family have CAS - before - RAS , RAS -only refresh and Hidden refresh
capabilities.
Two access modes are supported by this device: Byte access and Word access. Use only one of the two CAS and leave
the other staying high will result in a BYTE access. WORD access happens when two CAS ( CASL , CASH ) are used.
CASL transiting low during READ or WRITE cycle will output or input data into the lower byte (IO0~IO7), and CASH
transiting low will output or input data into the upper byte (IO8~15).
PIN ASSIGNMENT
SOJ Top View
TSOP (TypeII) Top View
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VSS
39 I/O15
38 I/O14
37 I/O13
36 I/O12
35 VSS
34 I/O11
33 I/O10
32 I/O9
31 I/O8
30 N C
29 CASL
28 CASH
27 OE
26 A8
25 A7
24 A6
23 A5
22 A4
21 VSS
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VSS
39 I/O15
38 I/O14
37 I/O13
36 I/O12
35 VSS
34 I/O11
33 I/O10
32 I/O9
31 I/O8
30 N C
29 CASL
28 CASH
27 OE
26 A8
25 A7
24 A6
23 A5
22 A4
21 VSS
Elite Memory Technology Inc
Publication Date: Aug. 2005
Revision : 1.4
1/16

1 page




M11L416256SA pdf
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EliteMT
(Continued)
PARAMETER
SYMBOL
Read Command Hold Time Reference to CAS
Read Command Hold Time Reference to RAS
CAS to Output in Low-Z
Output Buffer Turn-off Delay From CAS or
RAS
Output Buffer Turn-off to OE
Write Command Setup Time
Write Command Hold Time
Write Command Hold Time(Reference to RAS )
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Setup Time
Data-in Hold Time
Data-in Hold Time (Reference to RAS )
RAS to WE Delay Time
Column Address to WE Delay Time
CAS to WE Delay Time
Transition Time (rise or fall)
Refresh Period (512 cycles)
RAS to CAS Precharge Time
CAS Setup Time(CBR REFRESH)
CAS Hold Time(CBR REFRESH)
OE Hold Time From WE During
Read-Mode-Write Cycle
OE Low to CAS High Setup Time
OE High Hold Time From CAS High
OE Precharge Time
OE Setup Prior to RAS During Hidden
Refresh Cycle
Last CAS Going Low to First CAS
Returning High
Data Output Hold After CAS Returning Low
Output Disable Delay From WE
Self Refresh RAS Low Pulse width
Self Refresh RAS High Precharge Time
Self Refresh CAS Hold Time
tRCH
tRRH
tCLZ
tOFF1
tOFF2
tWCS
tWCH
tWCR
tWP
tRWL
tCWL
tDS
tDH
tDHR
tRWD
tAWD
tCWD
tT
tREF
tRPC
tCSR
tCHR
tOEH
tOES
tOEHC
tOEP
tORD
tCLCH
tCOH
tWHZ
tRASS
tRPS
tCHS
-35
MIN MAX
0
0
3
3 15
8
0
5
30
5
9
7
0
5
30
51
34
26
2.5 50
8
10
10
10
4
4
2
2
0
5
3
37
100
65
-50
M11L416256SA
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
NOTES
9,15,19
9
20
10,17,20
17,26
11,15,18
15,25
15
15
15
15,19
12,20
12,20
11
11
11,18
2,3
1,18
1,19
16
21
27,28
27,28
27,28
Elite Memory Technology Inc
Publication Date: Aug. 2005
Revision : 1.4
5/16

5 Page





M11L416256SA arduino
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EliteMT
M11L416256SA
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE
(Psuedo READ-MODIFY-WRITE)
VIH
RAS VIL
VIH
CASL,CASH VIL
VIH
ADDR VIL
VIH
WE VIL
VI/OH
I/O VI/O L
VIH
OE VIL
tRASC
tCRP
tRCD
tCSH
tPC
tCAS
tCP
tCAS
tCP
tCP
tRSH
tCAS
tRAD
tASR tRAH
tAR
tASC
tCAH
ROW
COLUMN(A)
tRCS
tASC tCAH
COLUMN(B)
tRCH
tRAL
tASC tCAH
COLUMN(N)
tWCS
tWCH
tAA
tRAC
tCAC
OPEN
tO AC
tACP
tAA
tCAC
tCOH
tWHZ
VALID DATA(A)
VALID
DATA(B)
tDS tDH
VALID
DATA IN
tRP
tCP
ROW
VIH
RAS VIL
VIH
CASL,CASH VIL
VIH
ADDR VIL
VOH
I/O VOL
RAS ONLY REFRESH CYCLE
(ADDR = A0~A8 ; OE , WE = DON’T CARE)
tCRP
tASR
tRAH
ROW
tRAS
tRC
OPEN
tRP
tRPC
ROW
DON'T CARE
UNDEFINED
Elite Memory Technology Inc
Publication Date: Aug. 2005
Revision : 1.4
11/16

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