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PDF IBM25PPC750FX Data sheet ( Hoja de datos )
| Número de pieza | IBM25PPC750FX | |
| Descripción | RISC Microprocessor | |
| Fabricantes | IBM Microelectronics | |
| Logotipo |  |
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® IBM PowerPC® 750FX RISC Microprocessor
Datasheet
(Support for 750FX Design Revision Level DD 2.X)
Version: 2.0
Preliminary
June 9, 2003
1 page  
www.DataSheet4U.com
Preliminary
.
DD 2.X
PowerPC 750FX RISC Microprocessor
1. General Information
The IBM PowerPC® 750FX RISC Microprocessor is a 32-bit implementation of the IBM PowerPC family of
reduced instruction set computer (RISC) microprocessors. This document contains pertinent physical and
electrical characteristics of the IBM PowerPC 750FX RISC Microprocessor Revision DD 2.X Single Chip
Modules (SCM). The IBM PowerPC 750FX RISC Microprocessor is also referred to as the 750FX throughout
this document.
1.1 Features
This section summarizes the features of the 750FX
implementation of the PowerPC Architecture™.
Major features of the 750FX include the following:
• Branch processing unit
– Four instructions fetched per clock
– One branch processed per cycle (plus
resolving two speculations)
– Up to one speculative stream in execution,
one additional speculative stream in fetch
– 512-entry branch history table (BHT) for
dynamic prediction
– 64-entry, 4-way set associative branch
target instruction cache (BTIC) for
eliminating branch delay slots
• Decode
– Register file access
– Forwarding control
– Partial instruction decode
• Load/store unit
– One cycle load or store cache access (byte,
half-word, word, double-word)
– Effective address generation
– Hits under miss (one outstanding miss)
– Single-cycle misaligned access within
double-word boundary
– Alignment, zero padding, sign extend for
integer register file
– Floating-point internal format conversion
(alignment, normalization)
– Sequencing for load/store multiples and
string operations
– Store gathering
– Cache and TLB instructions
– Big and little-endian byte addressing
supported
– Misaligned little-endian support in hardware
• Dispatch unit
– Full hardware detection of dependencies
(resolved in the execution units)
– Dispatch two instructions to six independent
units (system, branch, load/store, fixed-point
unit 1, fixed-point unit 2, or floating-point)
– 4-stage pipeline: fetch, dispatch, execute,
and complete
– Serialization control (predispatch,
postdispatch, execution, serialization)
• Fixed-point units
– Fixed-point unit 1 (FXU1): multiply, divide,
shift, rotate, arithmetic, logical
– Fixed-point unit 2 (FXU2): shift, rotate,
arithmetic, logical
– Single-cycle arithmetic, shift, rotate, logical
– Multiply and divide support (multi-cycle)
– Early out multiply
– Thirty-two 32-bit general purpose registers
• Floating-point unit
– Support for IEEE-754 standard single and
double-precision floating-point arithmetic
– Optimized for single-precision multiply/add
– Thirty-two, 64-bit floating point registers
– Enhanced reciprocal estimates
– 3-cycle latency, 1-cycle throughput,
single-precision multiply-add
– 3-cycle latency, 1-cycle throughput,
double-precision add
– 4-cycle latency, 2-cycle throughput,
double-precision multiply-add
– Hardware support for divide
– Hardware support for denormalized
numbers
– Time deterministic non-IEEE mode
• System unit
– Executes CR logical instructions and mis-
cellaneous system instructions
– Special register transfer instructions
Body_750FX_DS_DD2.X.fm.2.0
June 9, 2003
1. General Information
Page 3 of 63
5 Page 
www.DataSheet4U.com
Preliminary
DD 2.X
PowerPC 750FX RISC Microprocessor
3. Electrical and Thermal Characteristics
This section provides AC and DC electrical specifications and thermal characteristics for the 750FX.
3.1 DC Electrical Characteristics
The tables in this section describe the DC electrical characteristics for the 750FX.
Table 3-1. Absolute Maximum Ratings1
Characteristic
Symbol
1.8V
2.5V
3.3V
Unit Notes
Core supply voltage
VDD
-0.3 to 1.6
-0.3 to 1.6
-0.3 to 1.6
V 3, 4
PLL supply voltage
A1VDD, A2VDD
-0.3 to 1.6
-0.3 to 1.6
-0.3 to 1.6
V 3, 4, 5
60x bus supply voltage
OVDD
-0.3 to 2.0
-0.3 to 2.75
-0.3 to 3.7
V 3, 4
Input voltage
VIN
-0.3 to 2.0
-0.3 to 2.75
-0.3 to 3.7
V2
Storage temperature range
TSTG
-55 to 150
-55 to 150
-55 to 150
°C
Notes:
1. Functional and tested operating conditions are given in Table 3-2, “Recommended Operating Conditions” on page 10. Absolute
maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those
listed above may affect device reliability or cause permanent damage to the device.
2. Caution: Transient VIN overshoots of up to OVDD + 0.8V, with a maximum of 4.0V for 3.3V operation, and undershoots down to
GND - 0.8V, are allowed for up to 5ns.
3. Caution: OVDD must not exceed VDD/AVDD by more than 2.1V continuously. OVDD may exceed VDD/AVDD by up to 2.3V for up
to 20ms during power-on or power-off. OVDD must not exceed VDD/AVDD by more than 2.3V for any amount of time.
4. Caution: VDD/AVDD must not exceed OVDD by more than 1.0V continuously. VDD/AVDD may exceed OVDD by up to 1.6v for up
to 20ms during power-on or power-off. VDD/AVDD must not exceed OVDD by more than 1.6V for any amount of time.
5. Caution: AVDD must not exceed VDD by more than 0.5V at any time.
Body_750FX_DS_DD2.X.fm.2.0
June 9, 2003
3. Electrical and Thermal Characteristics
Page 9 of 63
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