DataSheet.es    


PDF GS864032T-xxxV Data sheet ( Hoja de datos )

Número de pieza GS864032T-xxxV
Descripción (GS8640xxGT-xxxV) 4M x 18/ 2M x 32/ 2M x 36 72Mb Sync Burst SRAMs
Fabricantes GSI Technology 
Logotipo GSI Technology Logotipo



Hay una vista previa y un enlace de descarga de GS864032T-xxxV (archivo pdf) en la parte inferior de esta página.


Total 23 Páginas

No Preview Available ! GS864032T-xxxV Hoja de datos, Descripción, Manual

www.DataSheet4U.com
Preliminary
GS864018/32/36T-xxxV
100-Pin TQFP
Commercial Temp
Industrial Temp
4M x 18, 2M x 32, 2M x 36
72Mb Sync Burst SRAMs
250 MHz167 MHz
1.8 V or 2.5 V VDD
1.8 V or 2.5 V I/O
Features
• FT pin for user-configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) operation
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• RoHS-compliant 100-lead TQFP package available
Functional Description
Applications
The GS864018/32/36T-xxxV is a 75,497,472-bit high
performance synchronous SRAM with a 2-bit burst address
counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPUs, the
device now finds application in synchronous SRAM
applications, ranging from DSP main store to networking chip
set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS864018/32/36T-xxxV operates on a 1.8 V or 2.5 V
power supply. All inputs are 1.8 V or 2.5 V compatible.
Separate output power (VDDQ) pins are used to decouple
output noise from the internal circuits and are 1.8 V or 2.5 V
compatible.
Pipeline
3-1-1-1
Flow Through
2-1-1-1
Parameter Synopsis
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
-250 -200 -167 Unit
2.5 3.0 3.5 ns
4.0 5.0 6.0 ns
340 290 260 mA
410 350 305 mA
6.5 7.5 8.0 ns
6.5 7.5 8.0 ns
245 220 210 mA
280 250 240 mA
Rev: 1.01 6/2006
1/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology

1 page




GS864032T-xxxV pdf
www.DataSheet4U.com
TQFP Pin Description
Symbol
A0, A1
A
DQA
DQB
DQC
DQD
NC
BW
BA, BB
BC, BD
CK
GW
E1, E3
E2
G
ADV
ADSP, ADSC
ZZ
FT
LBO
VDD
VSS
VDDQ
Type
I
I
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Preliminary
GS864018/32/36T-xxxV
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Data Input and Output pins
No Connect
Byte WriteWrites all enabled bytes; active low
Byte Write Enable for DQA, DQB Data I/Os; active low
Byte Write Enable for DQC, DQD Data I/Os; active low
Clock Input Signal; active high
Global Write EnableWrites all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.01 6/2006
5/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology

5 Page





GS864032T-xxxV arduino
www.DataSheet4U.com
Simplified State Diagram with G
Preliminary
GS864018/32/36T-xxxV
X
Deselect
WR
WR
X
First Write
CW
R
CR
W First Read X
CW CR
W
X
R
Burst Write
CR
CW
R
W Burst Read X
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.01 6/2006
11/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology

11 Page







PáginasTotal 23 Páginas
PDF Descargar[ Datasheet GS864032T-xxxV.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
GS864032T-xxx(GS8640xxT) 4M x 18/ 2M x 32/ 2M x 36 72Mb Sync Burst SRAMsGSI Technology
GSI Technology
GS864032T-xxxV(GS8640xxGT-xxxV) 4M x 18/ 2M x 32/ 2M x 36 72Mb Sync Burst SRAMsGSI Technology
GSI Technology

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar