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PDF P10C68 Data sheet ( Hoja de datos )
| Número de pieza | P10C68 | |
| Descripción | CMOS / SNOS NVSRAM | |
| Fabricantes | GEC Plessey Semiconductors | |
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P10C68/P11C68
PRELIMINARY INFORMATION
DS3600-1.2 September 1992
P10C68/P11C68
(Previously PNC10C68 and PNC11C68)
CMOS/SNOS NVSRAM
HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM
(Supersedes DS3159-1.3, DS3160-1.3, DS3234-1.1, DS3235-1.1)
The P10C68 and P11C68 are fast static RAMs (35 and 45
ns) with a non-volatile electically-erasable PROM (EEPROM)
cell incorporating in each static memory cell. The SRAM can
be read and written an unlimited number of times while
independent non-volatile data resides in PROM.
On the P10C68 data may easily be transferred from the
SRAM to the EEPROM (STORE) and from the EEPROM back
to the SRAM ( RECALL) using the NE (bar) pin. The Store and
Recall cycles are initiated through software sequences on the
P11C68. These devices combine the high performance and
ease of use of a fast SRAM with the data integrity of non-
volatility.
The P10C68 and P11C68 feature the industry standard
pinout for non-volatile RAMs in a 28-pin 0.3-inch plastic and
ceramic dual-in-line packages.
FEATURES
I Non-Volatile Data Integrity
I 10 year Data Retention in EEPROM
I 35ns and 45ns Address and Chip Enable Access Times
I 20ns and 25ns Output Enable Access
I Unlimited Read and Write to SRAM
I Unlimited Recall Cycles from EEPROM
I 104 Store Cycles to EEPROM
I Automatic Recall on Power up
I Automatic Store Timing
I Hardware Store Protection
I Single 5V ± 10% Operation
I Available in Standard Package 28-pin 0.3-inch DIL
plastic and ceramic
I Commercial and Industrial temperature ranges
ORDERING INFORMATION
(See back page)
NE
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 W
26 NC
25 A8
24 A9
23 A11
22 G
21 A10
20 E
19 DQ7
18 DQ6
17 DQ5
16 DQ4
15 DQ3
Pin 1
Pin 1
Pin Name
A0 - A12
W
DQ0 - DQ7
E
G
VCC
VSS
NE
N/C
Function
Address inputs
Write enable
Data in/out
Chip enable
Output enable
Power (+5V)
Ground
Non volatile enable
No connection
P10C68
P11C68
Figure 1. Pin connections - top view.
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SRAM MEMORY OPERATION
Test conditions (unless otherwise stated):
Commercial and Industrial Temperature Range
Tamb = -40°C to + 85°C, Vcc = + 5V ± 10%
READ CYCLES 1 AND 2 (See note 8)
P10C68/P11C68
Symbol
Standard Alternative
Parameter
tELQV
tAVAV
tAVQV
tGLQV
tAXQX
tELQX
tEHQZ
tGLQX
tGHQZ
tELICCH
tEHICCL
tWHQV
tACS
tRC
tAA
tOE
tOH
tLZ
tOHZ
tOLZ
tHZ
tPA
tPS
tWR
Chip enable access time
Read cycle time
Address access time
Output enable to data valid
Output hold after address change
Chip enable to output active
Chip disable to output inactive
Output enable to output active
Outout disable to output inactive
Chip enable to power active
Chip disable to power standby
Write recovery time
P10C68-35
P11C68-35
Min. Max.
35
35
35
20
5
5
20
0
15
0
25
45
P10C68-45
P11C68-45
Min. Max.
45
45
45
25
5
5
25
0
20
0
25
55
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
9
10
11
11
12
12
NOTES
8. E (bar), G (bar) and W (bar) must make the transition between VIH(min) to VIL(max), or VIL(max) to VIH(min) in a
monotonic fashion. NE (bar) must be ≥ VIH during entire cycle.
9. For READ CYCLE 1 and 2, W (bar) and NE (bar) must be high for entire cycle.
10. Device is continuously selected with E (bar) low, and G (bar) low.
11. Measured ±200mV from steady state output voltage. Load capacitance is 5pF.
12. Parameter guaranteed but not tested.
ADDRESS
DQ (DATA OUT)
W
tAXQX
tWHQV
tAVAV
tAVQV
DATA VALID
Figure 4. READ CYCLE 1 timing diagram (see notes 9 and 10).
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NE
G
tGLNL
tNLHN
P10C68/P11C68
W tWHNL
E
DQ
(DATA
OUT)
tELNL
tNLQZ
tNLQX
HIGH IMPEDANCE
Figure 11. P10C68 RECALL CYCLE 1: NE (bar) controlled timing diagram (see note 16).
tNLEL
NE
tGLEL
G
W
E
DQ
(DATA
OUT)
tWHEL
HIGH IMPEDANCE
tELNH
tELQX2
Figure 12. P10C68 RECALL CYCLE 2: E (bar) controlled timing diagram (see note 16).
NE
G
W
E
DQ
(DATA
OUT)
tNLGL
tWHGL
tELGL
HIGH IMPEDANCE
tGLNH
tGLQX2
Figure 13. P10C68 RECALL CYCLE 3: E (bar) controlled timing diagram (see note 16).
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