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PDF 29LV160DB Data sheet ( Hoja de datos )

Número de pieza 29LV160DB
Descripción AM29LV160DB
Fabricantes AMD 
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Am29LV160D
Data Sheet
RETIRED
PRODUCT
This product has been retired and is not recommended for designs. For new and current designs,
S29AL016D supersedes Am29LV160D and is the factory-recommended migration path for this
device. Please refer to the S29AL016D data sheet for specifications and ordering information. Avail-
ability of this document is retained for reference and historical purposes only.
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number 22358 Revision B Amendment 7 Issue Date May 5, 2006

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29LV160DB pdf
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DATA
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Am29LV160D Device Bus Operations ................................9
Word/Byte Configuration .......................................................... 9
Requirements for Reading Array Data ..................................... 9
Writing Commands/Command Sequences .............................. 9
Program and Erase Operation Status .................................... 10
Standby Mode ........................................................................ 10
Automatic Sleep Mode ........................................................... 10
RESET#: Hardware Reset Pin ............................................... 11
Output Disable Mode .............................................................. 11
Table 2. Sector Address Tables (Am29LV160DT) ..........................12
Table 3. Sector Address Tables (Am29LV160DB) ..........................13
Autoselect Mode ..................................................................... 14
Table 4. Am29LV160D Autoselect Codes (High Voltage Method) ..14
Sector Protection/Unprotection ............................................... 14
Temporary Sector Unprotect .................................................. 15
Figure 1. Temporary Sector Unprotect Operation........................... 15
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 16
Common Flash Memory Interface (CFI) . . . . . . . 17
Table 5. CFI Query Identification String ..........................................17
Table 6. System Interface String .....................................................18
Table 7. Device Geometry Definition ..............................................18
Table 8. Primary Vendor-Specific Extended Query ........................19
Hardware Data Protection ...................................................... 19
Low VCC Write Inhibit .............................................................. 19
Write Pulse “Glitch” Protection ............................................... 19
Logical Inhibit .......................................................................... 19
Power-Up Write Inhibit ............................................................ 19
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 20
Reading Array Data ................................................................ 20
Reset Command ..................................................................... 20
Autoselect Command Sequence ............................................ 20
Word/Byte Program Command Sequence ............................. 20
Unlock Bypass Command Sequence ..................................... 21
Figure 3. Program Operation .......................................................... 21
Chip Erase Command Sequence ........................................... 21
Sector Erase Command Sequence ........................................ 22
Erase Suspend/Erase Resume Commands ........................... 22
Figure 4. Erase Operation............................................................... 23
Command Definitions ............................................................. 24
Table 9. Am29LV160D Command Definitions ................................24
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 25
DQ7: Data# Polling ................................................................. 25
Figure 5. Data# Polling Algorithm ................................................... 25
RY/BY#: Ready/Busy# ........................................................... 26
DQ6: Toggle Bit I .................................................................... 26
DQ2: Toggle Bit II ................................................................... 26
Reading Toggle Bits DQ6/DQ2 .............................................. 26
Figure 6. Toggle Bit Algorithm......................................................... 27
SHEET
DQ3: Sector Erase Timer ....................................................... 28
Table 10. Write Operation Status ................................................... 28
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 29
Figure 7. Maximum Negative Overshoot Waveform ...................... 30
Figure 8. Maximum Positive Overshoot Waveform........................ 30
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 30
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 9. ICC1 Current vs. Time (Showing Active and
Automatic Sleep Currents) ............................................................. 32
Figure 10. Typical ICC1 vs. Frequency ........................................... 32
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 11. Test Setup..................................................................... 33
Table 11. Test Specifications ......................................................... 33
Figure 12. Input Waveforms and Measurement Levels ................. 33
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34
Read Operations .................................................................... 34
Figure 13. Read Operations Timings ............................................. 34
Hardware Reset (RESET#) .................................................... 35
Figure 14. RESET# Timings .......................................................... 35
Word/Byte Configuration (BYTE#) ........................................ 36
Figure 15. BYTE# Timings for Read Operations............................ 36
Figure 16. BYTE# Timings for Write Operations............................ 36
Erase/Program Operations ..................................................... 37
Figure 17. Program Operation Timings.......................................... 38
Figure 18. Chip/Sector Erase Operation Timings .......................... 39
Figure 19. Data# Polling Timings (During Embedded Algorithms). 40
Figure 20. Toggle Bit Timings (During Embedded Algorithms)...... 40
Figure 21. DQ2 vs. DQ6 for Erase and
Erase Suspend Operations ............................................................ 41
Figure 22. Temporary Sector Unprotect/Timing Diagram .............. 41
Figure 23. Sector Protect/Unprotect Timing Diagram .................... 42
Figure 24. Alternate CE# Controlled Write Operation Timings ...... 44
Erase and Programming Performance . . . . . . . 45
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 45
TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 45
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 46
TS 048—48-Pin Standard TSOP ............................................ 46
TSR048—48-Pin Reverse TSOP ........................................... 47
FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
8 x 9 mm ................................................................................ 48
SO 044—44-Pin Small Outline Package ................................ 49
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 50
Revision A (January 1999) ..................................................... 50
Revision A+1 (April 19, 1999) ................................................. 50
Revision B (November 23, 1999) ............................................ 50
Revision B+1 (February 22, 2000) .......................................... 50
Revision B+2 (November 7, 2000) ......................................... 50
Revision B+3 (November 10, 2000) ....................................... 50
Revision B+4 (April 5, 2004) ................................................... 50
Revision B+5 (June 4, 2004) .................................................. 50
Revision B+6 (October 7, 2004) ............................................. 50
Revision B7 (May 5, 2006) ..................................................... 50
22358B7 May 5, 2006
Am29LV160D
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29LV160DB arduino
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DATA SHEET
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function
of the device. Table 1 lists the device bus operations,
the inputs and control levels they require, and the re-
sulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29LV160D Device Bus Operations
Read
Write
Operation
Standby
Output Disable
Reset
Sector Protect (Note 2)
CE# OE# WE# RESET#
L LH
H
L HL
H
VCC ±
0.3 V
X
X
VCC ±
0.3 V
L HH
H
X XX
L
L HL
VID
Sector Unprotect (Note 2) L H L
Temporary Sector
Unprotect
X XX
VID
VID
Addresses
(Note 1)
AIN
AIN
X
X
X
Sector Address,
A6 = L, A1 = H,
A0 = L
Sector Address,
A6 = H, A1 = H,
A0 = L
AIN
DQ0–
DQ7
DOUT
DIN
DQ8–DQ15
BYTE#
BYTE#
= VIH
= VIL
DOUT DQ8–DQ14 = High-Z,
DIN DQ15 = A-1
High-Z High-Z
High-Z
High-Z High-Z
High-Z High-Z
High-Z
High-Z
DIN X
X
DIN X
DIN DIN
X
High-Z
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A19:A0 in word mode (BYTE# = VIH), A19:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the byte or word configura-
tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and con-
trolled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-
main at VIH. The BYTE# pin determines whether the
device outputs array data in words or bytes.
The internal state machine is set for reading array
data upon device power-up, or after a hardware re-
set. This ensures that no spurious alteration of the
memory content occurs during the power transition.
No command is necessary in this mode to obtain
array data. Standard microprocessor read cycles that
assert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 13 for the timing diagram. ICC1 in
the DC Characteristics table represents the active cur-
rent specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
22358B7 May 5, 2006
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