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PDF M32186 Data sheet ( Hoja de datos )
| Número de pieza | M32186 | |
| Descripción | single-chip RISC microcomputer | |
| Fabricantes | Renesas | |
| Logotipo |  |
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32186 Group
32-BIT RISC MICROCOMPUTER
REJ03B0116-0100Z
Rev.1.00
Dec 01, 2004
Description
The 32186 Group is a 32-bit single-chip RISC microcomputer with built-in flash memory. To accomplish high-
precision arithmetic operations, it incorporates a fully IEEE754 compliant, single-precision FPU.
This microcomputer contains a variety of peripheral functions. With the software necessary to run these peripheral
functions stored in its large-capacity flash memory, this microcomputer meets the needs of application systems for
high functionality, high-performance arithmetic capability, and sophisticated control, thereby adaptation to the
embedded applications can be easily configured.
Table 1.0.1 Product List
Type name
ROM
capacity
RAM
capacity
Frequency
Power supply voltage
at single-
supply
at double-
supplies
Temperature range
(Note 1)
M32186F8VFP 1 Mbytes 64 Kbytes
80MHz
5V or 3.3V 5V, 3.3V
-40°C to +125°C
Note 1: This does not guarantee continuous operation and there is a limitation on the length of use (temperature
profile).
Features
• CPU .............................. M32R-FPU core
(M32R Family common instruction set + single-precision FPU / bit manipulation instructions)
• Pipeline structure ............................................................................................................................. 6-stage structure
• Instruction set .................................................................................... 100 discrete instructions / 6 addressing modes
• Instruction format ............................................................................................................................. 6 bit/32-bit length
• Built-in multiplier-accumulator (DSP function instructions)
• Minimum instruction execution time ....................................................... 12.5ns (at f(CPUCLK) = 80 MHz operation)
• Built-in flash memory
• Built-in RAM
• Virtual-flash emulation function .................................................................................................. 8 Kbytes x 8 blocks
• Interrupt controller .............................................................................................. 41 interrupt sources, 8 priority levels
• Wait controller ........................................... can be extended 0-15 wait cycles and external signal for each of 4 areas
• I/O port .......................................................................................................... 97 ports (selectable from 3 input levels)
• External interrupt input pin ............................................................................................................................... 27 pins
• DMAC ...................................................................................................................................................... 10 channels
• Multijunction timers (MJT) ........................................................................................................................ 55 channels
• A/D converter ................................................................................. 16 channels 10-bit converter (sample & hold x 2)
• Serial interface ............................ 4 channels (clock synchronous/asynchronous), 2 channels (clock synchronous)
• CAN (CAN Specification 2.0B active) ...................................................... 2 channels, each having 32 message slots
• Direct RAM Interface (DRI)
• Real-time debugger (RTD)
• Non-Break Debug (NBD)
• JTAG (boundary scan function)
• Debug interface common to the M32R Family (SDI: Scalable Debug Interface)
• Package ......................................................................................................................... 144 pin LQFP (0.5mm pitch)
Applications
Automobile equipment control (e.g., Engine, ABS, AT, CCD, and Radar sensing applications), industrial equipment
system control, and high-function OA equipment (e.g., PPC)
Since this group is under development, its specifications are subject to change.
Rev.1.00 Dec 01, 2004 Page 1 of 46
REJ03B0116-0100Z
1 page  
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32186 Group
1.2 Block Diagram
1.2 Block Diagram
Figure 1.2.1 shows a block diagram of the 32186. The features of each block are described in Table 1.2.1.
M32R-FPU Core
(Max. 80MHz)
Multiplier/Accumulator
(32 bits x 16 bits + 56 bits)
Single-precision FPU
(fully IEEE 754 compliant)
Internal Flash Memory
(1 Mbyte )
Non-Break Debug
(NBD)
Internal RAM
(64 Kbytes)
Real-Time
Debugger
(RTD)
Direct RAM
Interface
(DRI)
PLL Clock Generator
Internal Power Supply
Generator (VDC)
Internal Bus
Interface
DMAC
(10 channels)
Multijunction Timer
(MJT: 55 channels)
A/D Converter
(A/D0 : 10-bit converter, 16 channels)
Serial Interface
(6 channels)
Interrupt Controller
(8 levels)
Wait Controller
Full CAN
(2 channels)
External Bus
Interface
Data
Address
Input/output ports, 97 lines
Figure 1.2.1 Block Diagram of the 32186
Rev.1.00 Dec 01, 2004 Page 5 of 12
REJ03B0116-0100Z
5 Page 
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32186 Group
1.3 Pin Functions
Table 1.3.1 Description of Pin Functions (3 / 3)
Type
Pin Name
Signal Name
Input/Output Description
Real-time
debugger
(RTD)
RTDTXD
RTDRXD
RTDCLK
RTD transmit data Output
RTD received data Input
RTD clock input Input
Serial data output pin for the real-time debugger.
Serial data input pin for the real-time debugger.
Serial data transmit/receive clock input pin for the
real-time debugger.
RTDACK
RTD acknowledge Output
A low-level pulse is output from this pin
synchronously with the start clock for the real-time
debugger’s serial data output word. The low-level
pulse width indicates the type of command/data
received by the real-time debugger.
CAN
CTX0, CTX1
Transmit data
Output
This pin outputs data from the CAN module.
CRX0, CRX1
Received data
Input
This pin accepts as input the data for the CAN
module.
JTAG
JTMS
Test mode select Input
Test mode select input to control the state transition
of the test circuit.
JTCK
Test clock
Input
Clock input for the debug module and test circuit.
JTRST
Test reset
Input
Test reset input to initialize the test circuit
asynchronously with device operation.
JTDI
Test data input
Input
This pin accepts as input the test instruction code
or test data that is serially received.
JTDO
Test data output Output
This pin outputs the test instruction code or test
data serially.
NBD
NBDD0 –NBDD3 Command/Address/ Input/output NBD command, address, and data input/output
Data
pins.
NBDCLK
Synchronizing clock Input
input
NBD synchronizing clock input pin.
NBDSYNC#
Top of data input Input
This pin controls the start position of NBD data.
NBDEVNT#
Event output
Output
This pin is used for event output when an NBD
event occurs.
DRI
DD0–DD31
DD input
Input
DRI data input pin.
DIN0–DIN4
DIN input
Input
DRI event input pin.
Input/output P00–P07
ports
(Note 1)
P10–P17
P20–P27
Input/output port 0
Input/output port 1
Input/output port 2
Input/output Programmable input/output port.
Input/output
Input/output
P30–P37
Input/output port 3 Input/output
P41–P47
Input/output port 4 Input/output
P61–P63
Input/output port 6 Input/output
P70–P77
Input/output port 7 Input/output
P82–P87
Input/output port 8 Input/output
P93–P97
Input/output port 9 Input/output
P100–P107
Input/output port 10 Input/output
P110–P117
Input/output port 11 Input/output
P124–P127
Input/output port 12 Input/output
P130–P137
Input/output port 13 Input/output
P150, P153
Input/output port 15 Input/output
P174, P175
Input/output port 17 Input/output
P220,
P221 (Note 2),
P224, P225
Input/output port 22 Input/output
Note 1: Input/output ports 5, 14, 16 and 18−21 are nonexistent.
Note 2: P221 is input-only port.
Rev.1.00 Dec 01, 2004 Page 11 of 12
REJ03B0116-0100Z
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet M32186.PDF ] | |
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