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PDF TAA2009 Data sheet ( Hoja de datos )

Número de pieza TAA2009
Descripción DIGITAL AUDIO AMPLIFIER USING DIGITAL POWER PROCESSING
Fabricantes Tripath Technology 
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Tripath Technology, Inc. - Technical Information
TA A 2 0 0 9
STEREO 9W (8) CLASS-T™ DIGITAL AUDIO AMPLIFIER USING
DIGITAL POWER PROCESSING™ TECHNOLOGY
TECHNICAL INFORMATION
Revision 1.02 – May 2006
GENERAL DESCRIPTION
The TAA2009 is a 9W/ch continuous average two-channel Class-T Digital Audio Power Amplifier IC
using Tripath’s proprietary Digital Power Processing™ technology. The TAA2009, in a QFN package,
along with extremely high efficiency, allows for a very compact amplifier design. Class-T amplifiers
offer both the audio fidelity of Class-AB and the power efficiency of Class-D amplifiers.
APPLICATIONS
LCD TV’s
LCD Monitors
Plasma TV’s
Computer/PC Multimedia
Battery Powered Systems
BENEFITS
Fully integrated solution with FETs
Compact packaging and board design
Reduced system cost with no heat sink
Differential inputs minimize common-mode
noise
Dramatically improves efficiency versus Class-
AB
Signal fidelity equal to high quality linear
amplifiers
High dynamic range compatible with digital
media such as CD, DVD, and Internet audio
Capable of driving a wide range of load
impedances
Sophisticated pop reduction circuit
TYPICAL PERFORMANCE
THD+N versus Output Power
10 VDD = 12V
5
f = 1kHz
Gain1=0, Gain0=1
BW = 22Hz - 20kHz(AES17)
2
1
0.5
0.2
0.1
0.05
RL = 16
RL = 8
RL = 4
RL = 6
FEATURES
Class-T architecture
Single Supply Operation
“Audiophile” Quality Sound
0.05% THD+N @ 5W, 8
0.16% IHF-IM @ 1W, 8
6.4W @ 8, 0.1% THD+N
3.5W @ 16, 0.1% THD+N
High Power
10.6W @ 6, 10% THD+N
9W @ 8, 10% THD+N
5W @ 16, 10% THD+N
Extremely High Efficiency
90% @ 5W, 16
86% @ 9W, 8
Dynamic Range = 96 dB
Mute and Sleep modes
Improved turn-on & turn-off pop
suppression
Over-current protection with automatic
restart circuit
Over-temperature protection
Space saving 32-pin 8mm x 8mm x 1mm
QFN package with exposed pad
Filterless Operation Option
32-pin QFN
(Top View)
IN1P
V5D
GAIN0
DGND
REF
SLEEP
MUTE
FAULT
1
2
3
4
5
6
7
8
24 IN2P
23 AGND
22 GAIN1
21 5VGEN
20 VDDA
19 DCAP
18 CPUMP
17 SUB
0.02
0.01
1
2 3 4 5 6 7 8 9 10
Output Power (W)
20
1 TAA2009 –KLi/1.02/ 05.06

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TAA2009 pdf
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Tripath Technology, Inc. - Technical Information
PIN DESCRIPTION
Pin
1, 24
2, 28
3, 22
Function
IN1P, IN2P
V5D, V5A
GAIN0, GAIN1
4 DGND
5 REF
6 SLEEP
7 MUTE
8
9, 12
16, 13
10, 15
11, 14
17
18
19
20
21
23, 30
25, 32
26, 31
27
FAULT
OUTP1 & OUTM1
OUTP2 & OUTM2
VDD1, VDD2
PGND1, PGND2
SUB
CPUMP
DCAP
VDDA
5VGEN
AGND, AGND
IN2M, IN1M
C2, C1
INL
29 BIASCAP
Description
Positive audio input for channel 1 and channel 2
Digital 5VDC, Analog 5VDC
Gain select bits. GAIN0 is least significant bit. See Applications Information for
programmable gain values. Both GAIN 0 and GAIN1 have internal 50Kpull-
down resistors.
Digital Ground. Connect to AGND locally (near the TAA2009).
Internal reference voltage; approximately 1.0 VDC.
When set to logic high, device goes into low power mode. If not used, this pin
should be grounded
When set to logic high, both amplifiers are muted and in idle mode. When low
(grounded), both amplifiers are fully operational. If left floating, the device stays in
the mute mode. This pin should be tied to GND if not used.
A logic high output indicates an under-voltage condition, thermal overload, and an
output is shorted to ground, or another output.
Bridged output pairs
Supply pins for high current H-bridges, nominally 12VDC.
Power Grounds (high current)
Substrate connection. Connect to PGND.
Charge pump input (nominally 10V above VDDA)
Charge pump switching output pin. DCAP is a free running 350kHz square wave
between VDDA and DGND (12Vpp nominal).
Power supply for analog VDD circuitry. Connect to same supply as VDD1 and
VDD2.
Regulated 5VDC source used to supply power to the input section (pins 2 and 28).
Analog Ground. Connect all pins together directly at the TAA2009.
Negative audio input for channel 2 and channel 1.
Pop minimization capacitor. Use 10uF.
Modulation selection pin. Connecting the INL pin to a logic high level enables the
inductor-less mode. This mode allows the TAA2009 to be operated without an
output filter as the switching outputs are in phase with zero input. If INL is tied to
a logic low or left floating (pulled down via internal 50Kresistor to ground), the
INL mode will be disabled. This results in a differential output switching pattern
typical of previous Tripath generation parts such as TA2024 and TAA2008. The
state of the INL pin should only be changed with MUTE at a logic high state.
Input stage bias voltage (approximately 2.4VDC).
5 TAA2009 –KLi/1.02/ 05.06

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TAA2009 arduino
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Tripath Technology, Inc. - Technical Information
TYPICAL PERFORMANCE WITH SINGLE ENDED INPUTS AND
FILTERED OUTPUTS
THD+N versus Output Power
10 VDD = 12V
5
f = 1kHz
Gain1=0, Gain0=1
BW = 22Hz - 20kHz(AES17)
2
1
0.5
0.2
0.1
0.05
RL = 16
RL = 8
RL = 4
RL = 6
0.02
0.01
1
2 3 4 5 6 7 8 9 10
Output Power (W)
20
100
90
80
70
60
50
40
30
20
10
0
0
1
Efficiency versus Output Power
VDD = 12V
Rf=L1=k8Hz
BW = 22Hz - 20kHz(AES17)
2 3 4 5 6 7 8 9 10
Output Pow er (Per Channel) - W
+0
-10 19kHz, 20kHz, 1:1
-20
VDD = 12V
Po = 1W
-30 3R2Lk=F8FT
-40 FS = 65kHz
-50 BW = 22Hz - 80kHz
-60
-70
-80
-90
-100
-110
-120
-130
20
50 100
Intermodulation Distortion
200 500 1k 2k
Frequency (Hz)
5k
10k 20k 30k
Efficiency versus Output Power
100
90
80
70
60
50
40
30
20 VDD = 12V
10 Rf=L1=k6Hz
BW = 22Hz - 20kHz(AES17)
0
0 1 2 3 4 5 6 7 8 9 10 11 12
Output Pow er (Per Channel) - W
1
.5
VDD = 12V
Po = 1W
RL = 8
.2 BW = 22Hz - 22kHz
.1
0.05
THD+N versus Frequency
0.02
0.01
0.005
0.002
0.001
20
50 100 200
500 1k
2k
Frequency (Hz)
5k 10k 20k
Channel Separation versus Frequency
+0
-10 VDD = 12V
Po = 1W
-20 RL = 8
BW = 22Hz - 22kHz
-30
-40
-50
-60
-70
-80
-90
-100
-110
20
50 100 200
500 1k
2k
Frequency (Hz)
5k
10k 20k
11 TAA2009 –KLi/1.02/ 05.06

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